Qualcomm Incorporated

Google Inc.

Edwin Jose

Michael Drop

Marzio Pedrali-Noy

Xuhao Huang

Deepti Vijayalakshmi Sriramagiri

Donghyun Kim

Raghu Sankuratri

Ravi Jenkal

Tao Wang

Ivan Hugh McLean

Joshua Stubbs

Boris Andreev

Farrukh Aquil

Vinod Chamarty

Sean Sweeney

Trang Nguyen

Xin Kang

Andrew Torchalski

Kyle John Rupnow

Gopi Krishna Tummala

Kang Yang

Baranidharan Muthukumaran

Deepti Sriramagiri

This document describes apparatuses and techniques for enabling a user to authorize access to early boot debugging of hardware issues in a computing system. In general, responsive to a user consenting to early boot debugging, a debug reenable signal is set in nonvolatile storage. Upon reinitialization of the computing system and receipt of an early debugging request, if the debug reenable signal is detected and the early debugging request is authenticated, an early boot debugging system is enabled. The user consent to early boot debugging may circumvent the setting of a fuse that otherwise would prevent performance of early boot debugging.

Early boot debugging of hardware issues in a computing system

Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.

Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness

Micro-idle power in a subsystem of a portable computing device may be actively managed based on client voting. Each client vote may include a client activity status indication and a client latency tolerance indication. Votes are aggregated to provide an aggregate client latency tolerance, which may be used to obtain a set of micro-idle time values. Micro-idle timers in the subsystem may be set to associated micro-idle time values. The micro-idle timers determine whether one or more of the micro-idle time values have elapsed. A power management policy associated with each micro-idle time value determined to have elapsed may be applied to a portion of the subsystem.

Active power management in a computing device subsystem based on micro-idle duration

Various embodiments include methods and devices for implementing progressive flush of a cache memory of a computing device. Various embodiments may include determining an activity state of a region of the cache memory, issuing a start cache memory flush command in response to determining that the activity state of the region is idle, flushing the region in response to the start cache memory flush command, determining that the activity state of the region is active, issuing an abort cache memory flush command in response to determining that the activity state of the region is active, and aborting flushing the region in response to the abort cache memory flush command.

Progressive flush of cache memory

Some aspects of the disclosure include a self-refresh entry sequence for a memory, such as a DRAM, that may be used to avoid a frequency mismatch between a system processor and a system memory. The self-refresh entry sequence may signal the memory to reset the frequency set point state and default to the power-up state upon a self-refresh process exit. In another aspect, a new mode register may be used to indicate that the frequency set point needs to be reset after the next self-refresh entry command. In this aspect, the processor will execute a mode register write command followed by a self-refresh entry in response to the occurrence of a crash event. Then, the memory will reset to the default frequency set point by the end of self-refresh entry execution.

Systems, methods, and apparatus for frequency reset of a memory

A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles.

Refresh timer synchronization between memory controller and memory

A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

Low latency synchronization scheme for mesochronous DDR system

In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Growing community of inventors

San Diego, CA, United States of America

Edwin Jose