Intel Corporation

Nxp B.v.

Edwin Jan Van Dalen

Aleksandar Beric

Steven Roos

Martinus C Wezelenburg

Alexander Augusteijn

Rakefet Kol

Amit Gur

Abraham Jan De Bart

Paulus Wilhelmus Franciscus Gruijters

Tamir Klein

Radomir Jakovljevic

Dragan Milicev

Edward Thomas Grochowski

Zoran Zivkovic

Jarno Nikkanen

Moshe Maor

Dmitar Redzic

Paulus W F Gruijters

A processor includes a decode unit to decode a packed data alignment plus compute instruction. The instruction is to indicate a first set of one or more source packed data operands that is to include first data elements, a second set of one or more source packed data operands that is to include second data elements, at least one data element offset. An execution unit, in response to the instruction, is to store a result packed data operand that is to include result data elements that each have a value of an operation performed with a pair of a data element of the first set of source packed data operands and a data element of the second set of source packed data operands. The execution unit is to apply the at least one data element offset to at least a corresponding one of the first and second sets of source packed data operands. The at least one data element offset is to counteract any lack of correspondence between the data elements of each pair in the first and second sets of source packed data operands.

Packed data alignment plus compute instructions, processors, methods, and systems

An apparatus and method for performing FIR filtering and blending operations. A processor comprising: a decode unit to decode a packed N-tap finite impulse response (FIR) filter instruction, the packed N-tap FIR filter instruction to indicate one or more source packed data operands comprising a plurality of packed data elements, at least 3 filter coefficients, and a destination storage location, the plurality of packed data elements comprising data from a signal to be filtered and the plurality of filter coefficients specifying a filter function to be applied; and an execution unit comprising an FIR unit coupled with the decode unit, the FIR unit, in response to the packed N-tap FIR filter instruction being decoded by the decode unit, to perform at least N&#x2212;1 multiplications to generate at least N&#x2212;1 products, each of the multiplications comprising one of the filter coefficients multiplied by one of the packed data elements, the execution unit to combine the at least N&#x2212;1 products in accordance with a specified type of FIR filter being implemented to generate a result packed data element to be stored in the destination storage location.

Apparatus and method for performing horizontal filter operations

Techniques related to multi-block memory reads for image de-warping are discussed. Such techniques may include copying pixel data corresponding to overlapping regions of memory between adjacent image modification regions from a local buffer and retrieving pixel data corresponding to non-overlapping regions from external memory.

Multi-block memory reads for image de-warping

An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.

Electronic apparatus having parallel memory banks

A processor includes a decode unit to decode a packed finite impulse response (FIR) filter instruction that indicates one or more source packed data operands, a plurality of FIR filter coefficients, and a destination storage location. The source operand(s) include a first number of data elements and a second number of additional data elements. The second number is one less than a number of FIR filter taps. An execution unit, in response to the packed FIR filter instruction being decoded, is to store a result packed data operand. The result packed data operand includes the first number of FIR filtered data elements that each is to be based on a combination of products of the plurality of FIR filter coefficients and a different corresponding set of data elements from the one or more source packed data operands, which is equal in number to the number of FIR filter taps.

Packed finite impulse response (FIR) filter processors, methods, systems, and instructions

Technologies are presented that allow efficient pixel-based image and/or video warping and scaling. An image processing system may include a memory and an accelerator unit communicatively coupled with the memory. The accelerator unit may, based on configuration settings, receive, from a memory, at least a portion of an input image as an array of neighboring four-cornered shapes; and process each shape by: determining locations of an array of output pixels delineated by four corner locations of the shape via linearization; interpolating a value of each pixel of the array of output pixels; and storing the interpolated pixel values in the memory. For warping, the array of neighboring four-cornered shapes may include an array of neighboring distorted tetragons that approximate distortion of the input image, and the interpolated pixel values may represent a warped output image. For scaling, the array of neighboring four-cornered shapes may include an array of neighboring rectangles.

Pixel-based warping and scaling accelerator

Intelligent parametric scratchap memory architecture

A method, system, and article provide robust automatic exposure control using embedded data.

Robust automatic exposure control using embedded data

Consistent with an example embodiment, there is a signal processing circuit. Linking multiplexing (L-MUX) circuits, link respective pairs of stream processing circuits. Each L-MUX circuit is individually switchable to a normal mode and a replacement mode; in normal mode, it passes a first stream of samples values between the stream processing circuits in the respective pair of the L-MUX circuits; in replacement mode, it supplies successive sample values from a second stream from the communication structure to a receiving one of the stream processing circuits in the respective pair. A control circuit keeps a selectable one of the multiplexing circuits in the replacement mode so the selectable one of the L-MUX circuits passes a stream of successive samples from the second stream to the receiving one of the processing circuits in the respective pair of L-MUX circuits, while keeping at least part of the other L-MUX circuits in the normal mode.

Electronic stream processing circuit with test access

A receiver circuit has a chain of stream processing circuits (-)&#x2014;having control parameter inputs for receiving control parameter values. To facilitate design of circuits that receive data with a variable block size, an included control circuit () selects block sizes of blocks of samples in the respective streams of a plurality of the stream processing circuits (-), a control parameter value for each particular block. The control circuit transmits instructions specifying the selected block sizes and control parameter values to local control circuits (). Each local control circuit is coupled to the control circuit () and the control input of a respective corresponding stream processing circuit (-). Each local control circuit () receives at least part of the instructions and applies parameter values from the instructions to its corresponding stream processing circuit (-). The local control circuit () controls timing of control parameter updates using block sizes from the instructions.

Electronic stream processing circuit with locally controlled parameter updates, and method of designing such a circuit

An electronic circuit, in particular a receiver circuit contains a chain of stream processing circuits (-). The stream processing circuits (-) have control parameter inputs for receiving control parameter values. In order to facilitate design of circuits that receive data with a variable block size, a control circuit () is included that selects block sizes of blocks of samples in the respective streams of a plurality of the stream processing circuits (-), a control parameter value for each particular block. The control circuit transmits instructions that specify the selected block sizes and control parameter values to local control circuits (). Each local control circuit is coupled to the control circuit () and the control input of a respective corresponding stream processing circuit (-) from the chain. Each particular local control circuit () is arranged to receive at least part of the instructions and to apply parameter values from the instructions to its corresponding stream processing circuit (-). The particular local control circuit () controls timing of control parameter updates using block sizes from the instructions by counting off block size dependent time intervals between times points of successive control parameter updates. As a result there is no need to adapt the design of the stream processing circuits (-) to the block sizes.

Growing community of inventors

Eindhoven, Netherlands

Edwin Jan Van Dalen