Intel Corporation

Other

Edwin J Pole, Ii

Xia Dai

Gurbir Singh

Frank P Hart

Cau L Nguyen

John T Orton

Scott R Rushford

Raviprakash Nagaraj

Ravi Nagaraj

David S Bormann

Chao-Hsin Chi

Dong Tieu

Eric S Swartzendruber

A method and apparatus for facilitating direct access to a serial Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).

Method and apparatus facilitating direct access to a serial ATA device by an autonomous subsystem

Methods and apparatuses for reducing leakage power consumption in a processor

A voltage regulator may switch in an extra load when the voltage regulator changes from a higher to a lower output level in response to a processor change of state in a processor-based system. The additional load at the lower voltage level in the processor-based system may decrease the latency in the voltage level transistor, improving processor performance.

System for transitioning a processor from a higher to a lower activity state by switching in and out of an impedance on the voltage regulator

A method for incorporating bus ratio strap options in chipset logic. The method of one embodiment first fabricates a register and multiplexer in chipset logic. The register is programmed with a bus ratio setting. A bus ratio setting is selected to be the output from the multiplexer. The selected bus ratio setting is driven out from the multiplexer to output pins.

Incorporation of bus ratio strap options in chipset logic

A processor has an external pin that can be asserted to lock in new clock ratio information dynamically. A state machine of the processor defines a stop grant state that is utilized to halt the internal clocking signal of the processor. A storage location, such as a register, is utilized to load new clock frequency information into the clock generator circuit of the processor. De-asserting the external pin of the processor causes the processor to resume normal operations, but at the newly set clock frequency.

Apparatus and method for changing processor clock ratio settings

A system includes a component, a detector adapted to detect generation of a power management event, and a controller adapted to transition the component from a first performance mode to a lower activity state in response to the power management event. The controller is adapted to change a setting of the component to a second, different performance mode while the component is in the lower activity state. The power management event may be generated in response to a change in the system's power source, an over-temperature condition, or a user command.

Managing a system's performance state

A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The clock generator is reset by the clock frequency change indication to change the clock's frequency while the component is in the low activity state. Storage elements containing different values are selectable to set the clock frequency. The storage elements include fuse banks and input pins.

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Hillsboro, OR, United States of America

Edwin J Pole, Ii