Hughes Aircraft Company

Raytheon Company

Edwin A Kelley

Wade J Stone

Don C Devendorf

Kikuo Ichiroku

Donald C Chang

Roger N Kosaka

Randall L Conilogue

Howard H Baller

Roy S Komori

A digital receiver apparatus and method, designed for multiple simultaneous users, digitizes a received analog RF signal and tunes to multiple desired frequencies of the received signal on a time division multiplexed basis. After filtering by a finite impulse response (FIR) filter that also operates in time division multiplexing for multiple service bands, the selected signals are digitally demodulated and signal processed, again on a time-shared basis. Different service bands are accommodated at the same time by separate FIR filters, each including a coefficient memory for its particular service band. The multiplexed frequency signal for each band is multiplied by the coefficients of its respective FIR filter memory in a common complex multiplier. The results are demultiplexed and directed to respective accumulators for decimation in accordance with the FIR coefficient characteristics.

Multiple user digital receiver apparatus and method with time division

A transmit/receive element having a transmit/receive circuit that includes a variable frequency transmit phase lock loop and a variable frequency receive phase lock loop, and an output amplifier that receives a modulated transmit signal from the transmit phase lock loop for driving an antenna element. The transmit phase lock loop receives a feedback signal which is (a) the modulated transmit signal during receive intervals and (b) the output of the output amplifier during transmit intervals, such that the transmit phase lock loop is controlled by a feedback signal at all times.

Transmit and receive antenna element with feedback

Multiple simultaneous uses of a multi-service digital receiver are made possible with a single practical analog-to-digital converter by translating the various service bands in frequency to form a single, generally continuous composite service band in which substantial frequency gaps between the different services are eliminated. Bandwidth requirements are further reduced by a bandfolding technique in which at least one service waveband is divided about an intermediate mixing frequency, the divided portions are overlapped so that they collectively occupy a sub-waveband with a smaller bandwidth than the original band, and the mixing frequency is chosen such that user-selected frequencies do not interfere with other active frequencies. Interference between non-selected active frequencies is permissible and simply ignored.

Multi-band digital receiving apparatus and method with bandwidth

A digital receiver apparatus and method, designed for multiple simultaneous users, digitizes a received analog RF signal and performs multiple frequency translations of the signal so that desired stations are grouped into a common frequency band separate from the remaining stations. This frequency band is then isolated, and the individual selected stations are digitally separated, demodulated and processed to provide multiple simultaneous outputs. The frequency translations are preferably performed initially on a time multiplexed basis. Isolated station separation is performed either by time multiplexing, or by the use of multiple phase or tan locked loops.

Multiple user digital receiver apparatus and method with combined

A digital radio frequency (RF) or intermediate frequency (IF) receiver for frequency division multiplexed (FDM) signals contained in a predetermined FDM band including an RF amplifier, an RF bandpass anti-alias filter, and an analog-to-digital (A/D) converter. The sample frequency F.sub.s of the A/D converter is lower than the lowest frequency in the predetermined FDM band and is selected to meet certain specified conditions based on the passband and stop band edges of the anti-alias filter so that the output of the A/D converter contains a non-distorted aliased frequency down converted digital version of the predetermined FDM band which is located between 0 Hz and one-half the sampling frequency. A digital complex mixer responsive to the digital output of the A/D converter translates the spectrum of the sampled digital received signal to center the desired FDM channel at zero frequency (DC). Digital low pass filtering isolates the desired channel centered at DC, and a digital complex mixer can be used to translate the isolated selected channel to a predetermined IF frequency. The in-phase portion of the digital IF centered selected channel or the DC centered complex envelope selected channel can then be provided to appropriate demodulation or decoder networks.

Efficient digital frequency division multiplexed signal receiver

A digital transmitter/transceiver accommodates multiple simultaneous receiver and transmitter channels by time division multiplexing the tuning and modulation hardware. Only a single digital-to-analog converter is required for multiple channel transmission, and time multiplexing permits the use of only a single set of digital hardware.

Multiple use digital transmitter/transceiver with time multiplexing

A digital computing system comprises first, second, third, fourth, fifth, and sixth multi-bit binary signal sources and first and second binary adders. Each binary adder has a plurality of parallel stages equal in number to the bits of the signals. Each stage of each adder has a first full adder and a second full adder. Each full adder has an addend input, an augend input, a carry input, a sum output, and a carry output. In the first adder, the first source is connected to the addend input of the first full adder, the second source is connected to the augend input of the first full adder, the third source is connected to the carry input of the first full adder, the sum output of the first full adder is connected to the addend input of the second full adder, the carry output of the first full adder is connected to the carry input of the next higher order stage of the second full adder, and the fourth source is connected to the augend input of the second full adder. The full adders are implemented with low-level, non-saturating, bipolar differential logic circuitry, which greatly reduces the power dissipation at high data processing speeds. The circuitry is physically laid out on an integrated circuit chip so the stages within an adder are contiguous to each other in bit order and/or the corresponding stages of different adders are aligned with each other.

High speed digital computing system

The efficient high-speed N word comparator receives a plurality of digital inputs which are simultaneously compared by conducting a digital to analog conversion on each input signal and comparing the analog signals in a plurality of weighted analog comparators. Each comparator conducts a balance between an associated input signal and the remaining input signals providing an output indication if the associated signal is an extremum value. The outputs of the comparators are then encoded to provide an address of the digital input of the extremum value and to select the input value through a multiplexer. The address and the value are then provided to subsequent circuitry for processing. Simultaneous comparison of all signals provides significantly reduced ripple delay while reducing the requirements for hardware allowing monolithic implementation for a larger plurality of inputs.

Efficient high speed N-word comparator

A digital intermediate frequency (IF) receiver for frequency division multiplexed (FDM) signals including analog circuitry for receiving FDM signals and an analog-to-digital (A/D) converter for converting the received signals to a sampled digital received signal. A digital complex mixer responsive to the digital output of the A/D converter translates the spectrum of the sampled digital received signal to center the desired FDM channel at zero frequency (DC). Digital low pass filtering isolates the desired channel centered at DC, and a digital complex mixer can be used to translate the isolated selected channel to a predetermined IF frequency. The in-phase portion of the digital IF centered selected channel or the DC centered complex envelope selected channel can then be provided to appropriate demodulation or decoder networks.

A digital aperture synthesized radiometer for synthesizing the imaging an image scene. A plurality of antenna arrays receive radiation emitted or reflected from an scene, and an analog to digital coverter converts received radiation into digitized signals. A digital beamformer synthesizes the digitized signals to provide an image corresponding to the scene. The digital beamformer comprises individual digital beamformers which generate a set of fanbeam signals for each array. The beamformers provide for cross track imaging of the scene. A digital interferometer correlates corresponding pairs of fanbeam signals from the two sets of fanbeam signals to produce a chirp signal for each pair. A matched filter processes the chirp signals to transform each chirp signal into a corresponding image point of the scene. This provides for along track imaging of the scene. The beamformers include an amplitude weighting and data turning circuit to reduce fanbeam signal sidelobe levels and eliminate alternate mainlobes from the digitized radiation signals to reduce mainlobe widening. A fast Fourier transform circuit in the beamformers generally comprises a decimation-in-time algorithm implemented by means of a plurality of parallel and cascaded butterfly computation circuits. Image processing methods for achieving digital radiometry are also disclosed.

Aperture synthesized radiometer using digital beamforming techniques

According to the invention, a high-speed digital data communication system employs current mode circuitry as input and output devices at the ends of a transmission line, such as the interconnections between integrated circuit chips. Specifically, a current mode driver switch generates output current amplitudes responsive to a source of a digital signal representative of data to be transmitted. The switch output is connected to the input of a transmission line. The output of the transmission line is connected to the input of a receiving circuit that responds to the current amplitudes and has an input at an approximately constant voltage level. The receiving circuit is a transistor connected in a common base configuration. The emitter of the transistor is connected to the output of the transmission line. The base of the transistor is connected to a constant voltage source. A pulse shaper in the form of a Schmitt trigger has positive feedback from output to input. The described current mode circuitry is incorporated into an integrated circuit chip.

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Los Angeles, CA, United States of America

Edwin A Kelley