National Yang Ming Chiao Tung University

Industrial Technology Research Institute

Development Center for Biotechnology

Edward Yi Chang

Wei-Hua Chieng

Shyr-Long Jeng

Stone Cheng

Yueh-Chin Lin

Chih-Chiang Wu

Ching-Yao Liu

Shih-Chien Liu

Cheng-Shih Lee

Kuo-Bin Wang

Li-Chuan Tang

Wei-Cheng Wu

Li-Han Hsu

Chia-Hua Chang

Tsung-Lin Chen

Ruey-Bing Hwang

Yu-Lin Hsiao

Chieh-Hsi Chuang

Jessie Lin

Ping-Cheng Han

Shih-Hsuan Tang

Yueh-Tsung Hsieh

Ting-En Hsieh

Chia-Hsun Wu

Chung-Kai Huang

Jung-Chi Lu

Chun-Yen Chang

Mau-Chung Frank Chang

Chien-I Kuo

Che-Wei Chang

Muh-Wang Liang

Ming-Tsan Peng

Hsin Tsai

Chih-Yuan Tseng

Pang-Min Chiang

Lung-Shen Lin

Chih-Chao Yang

Yeong-Lin Lai

Tsung Hsi Yang

Bin-Han Lue

Guangli Luo

Heng-Tung Hsu

Chung Yen Chang

Kazumitsu Nakamura

Lu-Che Huang

Yue-Cin Lin

Huang-Choung Chang

Yun-Chi Wu

Shang-Wen Chang

Ke-Shian Chen

Huang-Ming Lee

Newton Tang

Shih-Ming Chiang

Szu-Pei Wu

You-Long Sie

Hwa-Yi Chen

Hsin-Hua Chou

Tzann-Shun Hwang

Jwu-Shen Hu

Chien-Hsun Chiang

Shin-Wei Huang

Rico Chang

Hung-Ping D Yang

Jui-Sheng Wu

A method of manufacturing a semiconductor device includes providing a substrate. A channel layer is formed on the substrate. A barrier layer is formed on the channel layer. A source and a drain are formed on the barrier layer. A recess is formed in the barrier layer, in which the recess has a bottom surface, and a portion of the barrier underneath the recess has a thickness. A first dielectric layer is formed to cover the bottom surface of the recess. A charge trapping layer is formed on the first dielectric layer. A first ferroelectric material layer is formed on the charge trapping layer. A second dielectric layer is formed on the first ferroelectric material layer. A second ferroelectric material layer is formed on the second dielectric layer. A gate is formed over the second ferroelectric material layer.

Method of manufacturing semiconductor device

A GaN transistor is provided, which comprises: a substrate; a GaN layer disposed on the substrate; a barrier layer disposed on the GaN layer; a source electrode disposed on the barrier layer; a drain electrode disposed on the barrier layer; a composite dielectric layer disposed on the barrier layer and comprising a first seed layer and a La-doped HZO layer, wherein the first seed layer comprises ZrO; and a gate electrode disposed on the composite dielectric layer.

Gallium nitride transistor

The present disclosure provides a fast charging driver. The fast charging driver is configured to charge a battery of an electronic device. The fast charging driver includes a fast charging circuit and a charging controller. The fast charging circuit includes a first depletion-type GaN transistor, a first enhancement-type field effect transistor, a second depletion-type GaN transistor and a second enhancement-type field effect transistor. The charging controller is configured to control the fast charging circuit to operate in a constant current mode or a constant voltage mode according to a battery level of the battery. By utilizing the first depletion-type GaN transistor and the second depletion-type GaN transistor with a characteristic of a relatively low switching loss, the power consumption during charging the battery by the fast charging driver is decreased to improve the charge speed.

Fast charging driver

An inductive resonant wireless charging system includes a resonant wireless charging transmitting device, a wireless charging relay device and an inductive wireless charging receiving device. The resonant wireless charging transmitting device transmits a high-frequency radio frequency wave. The wireless charging relay device receives the high-frequency radio frequency wave using an electromagnetic resonance way, and converts the high-frequency radio frequency wave into a low-frequency radio frequency wave to transmit the low-frequency radio frequency wave. The inductive wireless charging receiving device receives the low-frequency radio frequency wave in a manner of electromagnetic induction.

Inductive resonant wireless charging system, resonant wireless charging transmitting device, wireless charging relay device and inductive wireless charging receiving device

A semiconductor device includes a substrate, a channel layer, a barrier layer, a ferroelectric composite material layer, a gate, a source and a drain. The channel layer and the barrier layer having a recess are disposed on the substrate in sequence. The ferroelectric composite material layer including a first dielectric layer, a charge trapping layer, a first ferroelectric material layer, a second dielectric layer and a second ferroelectric material layer is disposed in the recess. The gate is disposed on the ferroelectric composite material layer. The source and the drain are disposed on the barrier layer.

Semiconductor device and method of manufacturing the same

A power module includes: a GaN transistor, an NMOS transistor, a first capacitor, a first diode and a second diode. The NMOS transistor is electrically connected to the GaN transistor. A negative electrode of the first capacitor is electrically connected to an anode of the first diode and a gate of the GaN transistor. A cathode of the second diode is electrically connected to a gate of the NMOS transistor. The power module further includes a power module control terminal electrically connected to an anode of the first capacitor and an anode of the second diode.

Power module

A control method of a minimum power input applicable to a wireless power transfer system including a power transmission unit and at least one power receiving unit is provided. The power transmission unit is electrically connected with a control voltage signal and an input voltage signal and accordingly generates the minimum power input. The power transmission unit transmits the minimum power input wirelessly through a wireless transmission to the at least one power receiving unit for receiving. By adjusting the input voltage signal, the duty ratio and resonant frequency of the control voltage signal, the present invention ensures an optimal power transmission efficiency of the wireless power transmission system. Moreover, parameters of a charge pump reservoir and gate driving circuit can be further designed in view of the trend feedback of its gate drive waveforms so as to optimize the effect of the proposed invention.

Control method of a minimum power input

A voltage-controlled varied frequency pulse width modulator is provided, including a frequency-regulating voltage output device which receives a determining voltage, decides a resonant frequency according to the determining voltage and outputs an oscillation signal having the resonant frequency. A duty-ratio-regulating voltage output device receives the oscillation signal and a reference signal to determine a duty ratio through an inverting closed loop, so as to adjust the oscillation signal to have the duty ratio. By employing the proposed voltage-controlled modulator circuit with tunable frequency and varied pulse width of the present invention, a modulation signal having the determined resonant frequency and duty ratio is obtained. Moreover, the present invention can be further combined with gate drive waveform trend feedback designs to achieve superior power transmission efficiency of a wireless power transmission system to optimize the inventive effect of the present invention.

Voltage-controlled varied frequency pulse width modulator

A semiconductor structure having a Si substrate heterointegrated with GaN and a method for fabricating the same is disclosed. The method uses a (100) silicon substrate to fabricate a hundred nanometer scale hole and uses wet etching to etch the silicon substrate, thereby exposing the (111) crystal surface of the silicon substrate. The (111) crystal surface is used as a nucleating crystal surface of an AlN buffer layer and GaN. When GaN is grown, silane is reacted with GaN to adjust the concentration of doping silicon atoms into GaN, thereby forming a semiconductor structure having a Si substrate heterointegrated with GaN.

Semiconductor structure having a Si substrate heterointegrated with GaN and method for fabricating the same

A silicon metal-oxide-semiconductor field effect transistor with a wide-bandgap III-V compound semiconductor drain and a method for fabricating the same are disclosed. The method fabricates a hundred nanometer-scale hole in a (100) silicon substrate to expose the (111) facet of the silicon substrate, which favors to use selective area growth to form lattice matched III-V materials with high quality.

Silicon metal-oxide-semiconductor field effect transistor (Si MOSFET) with a wide-bandgap III-V compound semiconductor group drain and method for fabricating the same

A structure of high electron mobility transistor growth on Si substrate and the method thereof, in particular used for the semiconductor device manufacturing in the semiconductor industry. The UHVCVD system was used in the related invention to grow a Ge film on Si substrate then grow the high electron mobility transistor on the Ge film for the reduction of buffer layer thickness and cost. The function of the Ge film is preventing the formation of silicon oxide when growing III-V MHEMT structure in MOCVD system on Si substrate. The reason of using MHEMT in the invention is that the metamorphic buffer layer in MHEMT structure could block the penetration of dislocation which is formed because of the very large lattice mismatch (4.2%) between Ge and Si substrate.

Structure of high electron mobility transistor growth on Si substrate and the method thereof

The present invention provides a current limit circuit apparatus, coupled with the gate of a GaN transistor. The current limit circuit comprises a diode, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor and a fourth resistor. The source and the drain of the first transistor couple with the diode. The source of the second transistor couples with the gate of the first transistor. The source of the first transistor couples with the first transistor. The source of the second transistor couples with the second resistor. The third resistor couples with the fourth resistor and the gate of the first transistor. The first transistor turned off and the gate current is limited. When the current of the gate of the GaN transistor exceeds the predetermined value, the breakdown voltage is increased by limiting the gate current.

Current limit circuit apparatus

A sun-chasing device is provided, including a base, a first transmitter disposed on the base, a second transmitter, a support, a carrier pivotally connected to the support for carrying a solar module, a first supporting component pivotally connected to the first transmitter and the carrier, and a second supporting component pivotally connected to the second transmitter and the carrier. The sun-chasing device has great rigidity and carrying ability against strong wind, and has great precision and rotation angle, such that a solar plate can precisely aim at sun for long time and thus the efficiency of a solar module is significantly increased.

Sun-chasing device

The present invention provides a high-side driver circuit including a power transistor, the first transistor, the second transistor, the second capacitor, the second diode, a start-up circuit. The start-up circuit is coupled between a resistor and the second capacitor to complete a gate driving circuit. And, the aforementioned resistor can either be the gate resistance of the power transistor or an external resistor. The design of start-up circuit enables the functionality of the bootstrap capacitor of being charged to a designate voltage level. Thus, the depletion-mode transistor can be controlled to turn on/off without a floating voltage source or a negative voltage source.

High-side driver circuit

The present invention provides a method for forming a multilayer substrate having a gallium nitride layer, wherein a mesh layer having a plurality of openings is formed on a substrate, and a buffer layer, three aluminum gallium nitride layers with different aluminum concentrations and a gallium nitride layer are formed in sequence on the substrate in the openings. The three aluminum gallium nitride layers with different aluminum concentrations are capable of releasing stress, decreasing cracks on the surface of the gallium nitride layer and controlling interior defects, such that the present invention provides a gallium nitride layer with larger area, greater thickness, no cracks and high quality for facilitating the formation of high performance electronic components in comparison with the prior art. The present invention further provides a multilayer substrate having a gallium nitride layer.

Multilayer substrate having gallium nitride layer and method for forming the same

Growing community of inventors

Hsinchu, Taiwan

Edward Yi Chang