Other

Edward Yan

Lyle E Adams

Michael Ou

An ATA/IDE host controllergenerated from an HDL design base and a default frequency configuration script is disclosed. The controller supports ATA/IDE interface communications at a user-selected default frequency of 33, 66, 100, or 133 Mhz and at frequencies other than the default frequency using a set of programmable override timing registers. An internal timing control moduleprovides either the default timing parameters or the override timing parameters to the IDE host interface, according to the programmable override control

Configurable advanced technology attachment/integrated drive electronics host controller with programmable timing registers that store timing parameters that control communications

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San Jose, CA, United States of America

Edward Yan