International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Other

Infineon Technologies Ag

Macronix International Co., Ltd.

Edward William Kiewra

Devendra K Sadana

Carl John Radens

Steven M Shank

Kuen-Ting Shiu

Yanning Sun

Roy Charles Iggulden

John J Ellis-Monaghan

Marwan H Khater

William R Tonti

Ping-Chuan Wang

Yusheng Bian

Amlan Majumdar

Cheng-Wei Cheng

Ronald G Filippi

Steven John Koester

Keith E Fogel

John C S Hall

Dechao Guo

Shu-Jen Han

Joel Pereira De Souza

Solomon Assefa

Chandrasekhar Narayan

Shahab Siddiqui

Masaharu Kobayashi

Christopher Carr Parks

Axel Christoph Brintzinger

Abdelsalam A Aboketaf

Brett T Cucci

Zachary E Berndlmaier

Jeffrey P Gambino

Jack Allan Mandelman

Chung H Lam

Rajiv V Joshi

Yun-Yu Wang

Kaushik Chanda

Alessandro Cesare Callegari

Katherina E Babich

Jing Li

James J Demarest

Jens Hofrichter

Zhihong Chen

Antonio La Porta

Uzma B Rana

Daniel S Jubin

Christopher Adam Feild

Carol Reinholm

Ghavam G Shahidi

Daniel C Edelstein

Toshiharu Furukawa

Hsiang-Lan Lung

Ramachandra Divakaruni

Erh-Kun Lai

Stephen McConnell Gates

Supratik Guha

Robert K Leidy

Siva P Adusumilli

Dirk Pfeiffer

Ramachandran Muralidhar

Jason Scott Orcutt

Xuefeng Liu

Satyanarayana Venkata Nitta

Jon Alfred Casey

Vincent James McGahay

William M Green

Jean Fompeyrine

Mark Levy

Karen A Nummy

Roderick Alan Augur

Robert L Sandstrom

Kenneth John Giewont

Alfred Wagner

Thomas Benjamin Faure

Mary Elizabeth Weybright

Norma Edith Sosa Cortes

David J Webb

Szu-Lin Cheng

Michael J Hauser

Ronald Gene Filippi, Jr

Robert Daniel Edwards

Louis M Kindt

Ishtiaq Ahsan

William Joseph Ferrante

Stephen K Loh

Peter H Bartlau

Sunoo Kim

The present disclosure relates to semiconductor structures and, more particularly, to hybrid edge couplers with voids and methods of manufacture. The structure includes: a dielectric material; at least one waveguide structure embedded within the dielectric material; and at least one airgap within the dielectric material and extending along a length of the at least one waveguide structure.

Hybrid edge couplers with voids

Disclosed are embodiments of a photonic integrated circuit (PIC) structure with a waveguide core having tapered sidewall liner(s) (e.g., symmetric tapered sidewall liners on opposing sides of a waveguide core, asymmetric tapered sidewall liners on opposing sides of a waveguide core, or a tapered sidewall liner on one side of a waveguide core). In some embodiments, the tapered sidewall liner(s) and waveguide core have different refractive indices. In an exemplary embodiment, the waveguide core is a first material (e.g., silicon) and the tapered sidewall liner(s) is/are a second material (e.g., silicon nitride) with a smaller refractive index than the first material. In another exemplary embodiment, the waveguide core is a first compound and the tapered sidewall liner(s) is/are a second compound with the same elements (e.g., silicon and nitrogen) as the first compound but with a smaller refractive index. Also disclosed are method embodiments for forming such a PIC structure.

Photonic integrated circuit structure with at least one tapered sidewall liner adjacent to a waveguide core

Structures for an edge coupler of a photonics chip and methods of forming an edge coupler for a photonics chip. The structure includes a waveguide core on a dielectric layer, as well as an interconnect structure including a interlayer dielectric layer positioned over the dielectric layer and an opening penetrating through the interlayer dielectric layer to the waveguide core. A region of the interlayer dielectric layer is positioned to overlap with a portion of the waveguide core. The region of the interlayer dielectric layer has a surface that is rounded with a curvature.

Edge couplers including a rounded region adjacent to an opening in the interconnect structure

The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: a spiral fin structure comprising semiconductor substrate material and dielectric material; a photosensitive semiconductor material over sidewalls and a top surface of the spiral fin structure, the photosensitive semiconductor material positioned to capture laterally emitted incident light; a doped semiconductor material above the photosensitive semiconductor material; and contacts electrically contacting the semiconductor substrate material and the doped semiconductor material from a top surface thereof.

Photodiode and/or pin diode structures

Structures for a photodetector or terminator and methods of fabricating a structure for a photodetector or terminator. The structure includes a waveguide core, a light-absorbing layer having a sidewall, and a taper positioned adjacent to the sidewall of the light-absorbing layer. The taper extends laterally from the sidewall of the light-absorbing layer to overlap with the waveguide core, and the taper has a thickness that varies with position relative to the sidewall of the light-absorbing layer. For example, the thickness of the taper may decrease with increasing distance from the sidewall of the light-absorbing layer.

Photodetectors and terminators including a tapered thickness

Structures including a grating coupler and methods of fabricating a structure including a grating coupler. The structure includes structure includes a dielectric layer on a substrate, a first waveguide core positioned in a first level over the dielectric layer, and a second waveguide core positioned in a second level over the dielectric layer. The second level differs in elevation above the dielectric layer from the first level. The first waveguide core includes a tapered section. The structure further includes a grating coupler having a plurality of segments positioned in the second level adjacent to the second waveguide core. The segments of the grating coupler and the tapered section of the first waveguide core are positioned in an overlapping arrangement.

Optical components in the back-end-of-line stack of a photonics chip using plural cores vertically stacked

The invention relates to a method used in a photolithographic process comprising depositing a film of Atomic Layered Deposition (ALD) AlOon a photomask, subjecting said film of AlOon the photomask to a plasma treatment and then irradiating the deposited film of ALD AlOon the coated photomask at a wavelength of 193 nm.

Protection of photomasks from 193nm radiation damage using thin coatings of ALD Al2O3

Photodetector including: a waveguide of a waveguide material extending over a substrate; an insulating layer formed over the waveguide and having an opening exposing the waveguide; a photodetector layer formed over the insulating layer and into the opening so as to make contact with the waveguide, the photodetector layer having a first end at the opening and a second end distal from the opening, the photodetector layer being a gradient material of the waveguide material and germanium wherein a waveguide material portion of the gradient material varies from a maximum at the first end to a minimum at the second end and wherein a germanium portion of the gradient material varies from a minimum at the first end to a maximum at the second end; a photodetector region at the second end; and a photodetector layer extension extending at an angle from the photodetector layer at the second end.

Rapid melt growth photodetector

An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second III-V semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.

III-V field effect transistor on a dielectric layer

Photodetector structures and methods of manufacture are provided. The method includes forming undercuts about detector material formed on a substrate. The method further includes encapsulating the detector to form airgaps from the undercuts. The method further includes annealing the detector material causing expansion of the detector material into the airgaps.

Photodetector and methods of manufacture

Disclosed are a method of forming a photodetector and a photodetector structure. In the method, a polycrystalline or amorphous light-absorbing layer is formed on a dielectric layer such that it is in contact with a monocrystalline semiconductor core of an optical waveguide. The light-absorbing layer is then encapsulated in one or more strain-relief layers and a rapid melting growth (RMG) process is performed to crystallize the light-absorbing layer. The strain-relief layer(s) are tuned for controlled strain relief so that, during the RMG process, the light-absorbing layer remains crack-free. The strain-relief layer(s) are then removed and an encapsulation layer is formed over the light-absorbing layer (e.g., filling in surface pits that developed during the RMG process). Subsequently, dopants are implanted through the encapsulation layer to form diffusion regions for PIN diode(s). Since the encapsulation layer is relatively thin, desired dopant profiles can be achieved within the diffusion regions.

Photodetector methods and photodetector structures

A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.

Planar III-V field effect transistor (FET) on dielectric layer

A method of forming a high k gate stack on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AONprior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.

High &#x3ba; gate stack on III-V compound semiconductors

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Verbank, NY, United States of America

Edward William Kiewra