Cavium, Inc.

Raytheon Company

Edward Wade Thoenes

David Da-Wei Lin

Jonathan P Comeau

Matthew A Morton

David Lin

Thucydides Xanthopoulos

Vasudevan Kandadi

A byte lane of an integrated circuit including two data strobe loopback paths that allow external test signals to flow in and out of the integrated circuit through data strobe pins in two opposite directions. The integrated circuit includes a Feed Forward Equalization (FFE) path configured to send FFE signals output from the FFE logic via a transmitter set to a first data strobe interface during a normal operation. In a loopback test mode operation, a test signal can be supplied from a second data strobe interface and output to the first data strobe interface by reusing the FFE path. The second loopback path conversely allows a test signal to be routed from the first data strobe interface to the second.

External DQS bi-directional loopback with use of feed forward equalization path

A method and corresponding apparatus for aligning a data signal with a corresponding clock signal include oversampling the data signal based on the corresponding clock signal and generating corresponding data samples. An indication of skew between the data signal and the corresponding clock signal is detected based on data samples. A variable delay line coupled to the data signal is then adjusted based on the indication of skew detected. According to at least one example implementation, the data signal is oversampled based on the corresponding clock signal and multiple time-shifted versions of the corresponding clock signal. At least one signal of the corresponding clock signal and the multiple time-shifted versions of the corresponding clock signal is employed in sampling the data signal at a potential transition edge of the data signal.

Method and apparatus for aligning signals

A controller includes first and second functional units, first and second clock-signal sources that provide corresponding first and second clock signals that drive the first and second functional units respectively. The second clock-signal generates its second clock-signal based on the first clock-signal. The clock-retardation unit dynamically causes the second clock-signal to have a target time-domain offset relative to the first clock-signal.

Controlled dynamic de-alignment of clocks

An apparatus for controlling memory includes a memory controller, and a data interface that interfaces with and is in data communication with data lines, each having inherent skew. Each data line carries a data signal. The data lines connect the memory controller to the memory. The apparatus also includes data de-skewers, each associated with a corresponding data line, a strobe interface that interfaces with a strobe line that connects the memory controller to the memory and that applies a timing signal to the strobe line, and a strobe de-skewer connected to the strobe line. Each data de-skewer operates in read or write mode. A particular data line's data de-skewer applies a compensation skew to a data signal carried by that line.

Managing skew in data signals with adjustable strobe

An apparatus for data processing includes first and second functional units driven by corresponding first and second clock-signal sources, and a clock-retardation unit. The clock-retardation unit is configured to cause the second clock-signal to sustain a temporal offset that causes an offset between the first and second clock-signals to step toward a target time-domain offset between the first and second clock-signals.

Controlled multi-step de-alignment of clocks

An apparatus for controlling memory includes a memory controller, and an interface to data lines connecting it to memory. Each line carries a signal that corresponds to a bit to be written to memory. The interface includes, for each line, circuitry for transmitting a bit to memory via the line, and a data de-skewer. For each line, the de-skewer receives a first data signal that represents a bit to be written. Each line has an inherent skew. The de-skewer generates a second data signal by applying a skew to the first. A selected extent of skew increases a likelihood of sampling the second data signal during a data-valid window thereof. The same de-skewer receives and skews a first data bit read from the memory.

Managing skew in data signals

A method for controlling a memory includes causing a data de-skewer to operate in a writing mode, at the data de-skewer, receiving a first signal, and skewing the first data signal by a first compensation skew, causing the data de-skewer to operate in a reading mode, at the data de-skewer, receiving a second signal, and skewing the second signal by a second compensation skew, wherein the first signal is representative of a bit from a byte that is to be written to the memory, and wherein the second signal is representative of a bit from a byte that has been read from the memory.

Managing skew in data signals with multiple modes

A method of sampling data signals in response to a timing signal includes receiving data signals that are skewed relative to each other. Each data signal has a valid-data window having an extent such that, when a data signal is received, an invisible portion of the valid-data window is outside an observation window and a visible portion of the valid-data window is inside the observation window. The method further includes, for each of the data signals, identifying a designated location within the valid-data window that is part way across the extent of the valid-data window, and for each of the data signals, aligning the data signal such that the designated location aligns with the timing signal.

Variable strobe for alignment of partially invisible data signals

A phase shifter-attenuator system having: a controller for producing a digital word representative of a predetermined phase shift and attenuation provided to an input signal; and a phase shifter-attenuation section. The phase shifter-attenuation section includes: a phase rotator for providing one of a plurality combinations of phase shifts-attenuation states to the input signal selectively in accordance with one portion of the produced digital word; and an attenuation section for distributing the plurality of combinations of phase shift-attenuation states over a selected range of attenuations, such range being selected in accordance with a second portion of the produced digital word. The phase shifter-attenuator section provides one of a plurality of combinations of phase shift-attenuation states to the input signal selectively in accordance with one portion of the produced digital word, the combinations being distributed over a range of attentions selected in accordance with a second portion of the digital word.

Variable phase shifter-attenuator

A harmonic rejection mixer having a phase rotator fed by a local oscillator signal. The local oscillator signal has a reference frequency. The phase rotator produces a plurality of output signals, each one of the signals having a common frequency related to the reference frequency and having different relative phase shifts. A plurality of mixer sections, each one of the sections being fed an input signal and a corresponding one of the plurality of output signals mixes the local oscillator signal with the corresponding one of the plurality of output signals fed thereto. A combiner combines the mixer signal from the plurality of mixer sections into a composite output signal. A detector detects energy in a harmonic of the composite signal and for adjusting the output signal of the phase rotator to reduce the selected harmonic of the composite signal.

Harmonic reject mixer with active phase mismatch compensation in the local oscillator path

An amplifier having an input transmission network with a plurality of input transformers having serially coupled primary windings. Each one of the input transformers has a secondary winding magnetically coupled to a corresponding one of the primary windings. The amplifier includes an output transmission network having a plurality of output transformers having serially coupled secondary windings. Each one of the output transformers has a secondary winding magnetically coupled to a corresponding one of the primary windings. The amplifier includes a plurality of amplifier sections, each one the sections having an input connected to a corresponding one of the secondary windings of the input transformers and an output connected to a corresponding one of the primary windings of the output transformers. The input and output transmission networks are arranged to combine signals passing from an input to the input transmission network through the plurality of amplifier sections combine in-phase at an output of the output transmission section.

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Cambridge, MA, United States of America

Edward Wade Thoenes