International Business Machines Corporation

Edward W Conrad

Orest Bula

William C Leipold

Daniel C Cole

James Allan Bruce

John S Smyth

Michael Straight Hibbs

Joshua J Krueger

David V Horak

Chung H Lam

Jed Hickory Rankin

Edmund Juris Sprogis

Dale Warner Martin

Charles Arthur Whiting

Jacek G Smolinski

Paul D Sonntag

Daniel Boyd Sullivan

Craig E Schneider

David P Paul

Robert K Leidy

John Maxwell Cohn

Randy William Mann

Ning Lu

James Marc Leas

Timothy E Neary

Donald J Samuels

Andrew J Watts

Paul William Pastel

Arthur C Winslow

Archibald John Allen

Stephen E Knight

Charles J Parrish

Ronald E Chappelow

Shawn R Goddard

Edward Daniel Buker

James C Douglas

David A Ziemer

The subject matter disclosed herein relates to determining a lithographic set point using simulations of optical proximity correction verification. In one embodiment, a computer-implemented method of determining a lithographic tool set point for a lithographic process is disclosed. The method may include: providing a model of a production lithographic process including simulations of printed shapes; analyzing the model of the production lithographic process to determine whether a set of structures on a production mask used in the production lithographic process to create the printed shapes will fail under a plurality of set points; determining an operating region of set points where the set of structures on the production mask does not fail; and establishing a set point location within the operating region based upon a set point selection function.

Determining lithographic set point using optical proximity correction verification simulation

The present invention provides a method and computer program product for designing an electrically testable pattern that is based on patterns derived from the desired chip layout to be printed. Such electrical test patterns are based on the features within a region of influence around critical sites. The critical sites may be identified, for example, by processing the chip layout through an OPC verification tool that flags potential failure sites. The electrical test pattern is formed from features within an region of influence (ROI) around the critical site, and also include electrical feed lines at terminal ends of one or more features having an electrical characteristic that is sensitive to changes in the printed environment of the critical site. The feed lines may be locate on the same or a different layer than the critical site, depending on the chip design. The electrical pattern is further defined by retaining features within a second trim region such that the printed features within the ROI are not substantially modified by the absence of features outside the second trim region.

Method for creating electrically testable patterns

The invention relates to fitting a curve to a plurality of data points. A 'seed curve' is determined from a first set of data points selected from the plurality of data points. From the remaining data points, data points are individually selected and a determination is made for each selected data point as to whether the data point is acceptable to be included with the first set of data points. When a data point is determined to be acceptable, the data point is included with the first set of data points to form another set of data points. After each of the other data points are evaluated for inclusion with the first set of data points, a best fit curve is determined from a final set of data points.

System and method of curve fitting

An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.

Mask defect analysis system

Disclosed are a method and system for calibrating grid parameters for a photolithographic tool. One embodiment of the invention utilizes at least two artifacts located on the wafer stage. The artifacts are located outside of the area where a substrate would be placed. Typically, four artifacts are used, with two artifacts located along the same axis. The stage moves a first artifact to the alignment system and the system measures the location of the first artifact. The stage then moves the second artifact, which is on the same axis but on the other side of the wafer stage, under the alignment system and measures the location of the second artifact. This is repeated for the other two artifacts that line up in a second axis (i.e., perpendicular to the first axis). Grid offsets are calculated to provide, for example, grid magnification and rotation calibrations.

Method and apparatus to separate field and grid parameters on first level wafers

A system and method for optimizing metrology sampling rates in an advanced process control (APC) application. A method is provided for processing a run of workpieces, the method comprising the steps of: providing a database comprising subgroups of data representing characteristics from previously processed workpieces; selecting a first subgroup of data having characteristics that satisfy a predetermined criteria; determining processing conditions for a processing tool corresponding to said first subgroup of data; processing the run of workpieces with the process tool using the determined processing conditions; and measuring the run of workpieces according to a sampling rate determined from the first subgroup of data.

System and method for optimizing metrology sampling in APC applications

A method and structure for forming a sidewall image transfer conductor having a contact pad includes forming an insulator to include a recess, depositing a conductor around the insulator, and etching the conductor to form the sidewall image transfer conductor, wherein the conductor remains in the recess and forms the contact pad and the recess is perpendicular to the sidewall image transfer conductor.

Self-aligned contact areas for sidewall image transfer formed conductors

A system and method for optimizing a manufacturing process. The system comprises: a database of operational data gathered from previously performed manufacturing processes; a filtering system for filtering the database into a plurality of data subsets; a calculation system for calculating evaluation criteria for a selected data subset; an analysis system for determining if the evaluation criteria meets a set of predetermined requirements; and an iteration system that selects a new data subset if the selected data subset fails to provide evaluation criteria that meets the set of predetermined requirements.

System and method for optimizing manufacturing processes using real time partitioned process capability analysis

A method and apparatus for extracting two-dimensional image shapes from image data on a pixel array. The method comprises the steps of selecting intensity vs. pixel information in a plurality of directions in the vicinity of an edge of the image shape, and recognizing scans with sufficient contrast as containing edge information. Acceptable scans are subjected to an edge detection algorithm, the edge location is detected, and a locus of points is generated, from the detected edge values, that define the two-dimensional shape of the image. The edge detection algorithm may be a user defined edge detection algorithm that is tailored to the application. Also, in a preferred embodiment, the selecting step includes the step of selecting intensity vs. pixel information in at least four directions, and the plurality of directions are angularly spaced apart at least about 22 degrees. With one embodiment, one of these directions may be normal to an approximate edge location.

Method for measurement of full-two dimensional submicron shapes

A system and method of monitoring and predicting tool overlay settings comprise generating current lot information, generating historical data, categorizing (binning) the historical data into discrete exposure field size ranges, and predicting current lot tool overlay settings based on the current lot information and historical data. The method monitors the overlay errors during each lot pass through each lithographic process operation. Moreover, the method uses a feedback sorting criteria to monitor the tool overlay settings. Furthermore, the current lot information comprises lithographic field dimensions, wherein the lithographic field optics distortion data is derived from the current lithographic process tool. Additionally, the historical data comprises same-bin lithographic field size dimensions of previous lots, which statistically means the data is derived from the same (or similar) bin of like lots, on the current lithographic process tool.

Feedback method utilizing lithographic exposure field dimensions to predict process tool overlay settings

A method and structure for creating a photomask data set includes inputting a design data set, creating a simulated printed data set by applying a lithography simulation model to chosen levels of the design data set, merging each chosen level of the design data set with each corresponding level of the simulated printed data set in order to produce a merged design data set, applying at least one test to the merged design data set, correcting the design data set based on results of the test to produce a corrected design data set, repeating the creating of the simulated printed data, merging, applying the test and correcting using the corrected design data set until the corrected design data set passes the test, and outputting the corrected design data set as the photomask data set.

Interactive optical proximity correction design method

A method and system embodying the present invention for predicting systematic overlay affects in semiconductor lithography. This method is a feed-forward method, based on correlation of current and prior aligned levels, to predict optimum overlay offsets for a given lot. Instead of using population averaging, which ignores process variability, it acknowledges the variability and uses prior measurements to advantage. The principle, backed by production data, is that &ldquo;systematic&rdquo; overlay errors are just that: Image placement errors which persist through processing and will be predictable through time and processing.

Feed-forward lithographic overlay offset method and system

A method and structure for a photomask that includes a substrate having a first transmittance, a first pattern to be transferred to a photosensitive layer (the first pattern having a second transmittance lower than the first transmittance) and a second pattern having a third transmittance greater than the second transmittance and less than the first transmittance. The second pattern is adjacent at least a portion of the first pattern, and the substrate and the second pattern transmit light substantially in phase.

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Jeffersonville, VT, United States of America

Edward W Conrad