International Business Machines Corporation

Edward W Chencinski

Matthias Klein

Michael Jung

Philip A Sciuto

Martin Rehm

Michael James Becht

Xiaojin Wei

M Dean Sciacca

Craig A Bickelman

Seth R Greenspan

Michael F Fee

Bruce H Ratcliff

Eric N Lais

Carsten Otte

Ralf Winkelmann

Hanno Eichelberger

Daniel Francis Casper

Pasquale A Catalano

Peter Kenneth Szwed

Christopher J Colonna

Chin-Long Chen

Steven G Glassen

Marco Kraemer

John C Dayka

Vincenzo Condorelli

Stephen Robert Guendert

Timothy Gerard McNamara

Michael J Jordan

Klaus Werner

Thomas B Mathias

Robert R Livolsi

Joseph M Hoke

James Richard Coon

Garry Joseph Sullivan

Samir Kirit Patel

Neal T Christensen

Richard J Gusefski

Paul W Bond

Leonard L Fogell

Jeffrey C Bixler

The present disclosure relates to a method for a computer system comprising a plurality of processor cores including a first processor core and a second processor core, wherein a data item is exclusively assigned to the first processor core, of the plurality of processor cores, for executing an atomic primitive by the first processor core. The method includes receiving by the first processor core, from the second processor core, a request for accessing the data item, and in response to determining by the first processor core that the executing of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Method and processor system for executing a TELT instruction to access a data item during execution of an atomic primitive

In-line data packet transformations. A transformation engine obtains data to be transformed and determines a transformation to be applied to the data. The determining uses an input/output control block that includes at least one field to be used in determining the transformation to be applied. Based on determining the transformation to be applied, the transformation is performed.

In-line data packet transformations

The present disclosure relates to a method for a computer system comprising a plurality of processor cores, including a first processor core and a second processor core, wherein a cached data item is assigned to a first processor core, of the plurality of processor cores, for exclusively executing an atomic primitive. The method includes receiving, from a second processor core at a cache controller, a request for accessing the data item, and in response to determining that the execution of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Executing an atomic primitive in a multi-core processor system

A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Peripheral component interconnect express (PCIE) network with input/output (I/O) operation chaining to reduce communication time within execution of I/O channel operations

Peripheral component interconnect express (PCIE) network with input/output (I/O) chaining to reduce communication time within execution of I/O channel operations

Embodiments relate to controlling a temperature of a solid state memory device using queue depth management by monitoring an operating temperature of each of a plurality of solid state drives of the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds local device threshold values, the method includes receiving an indication that one or more local measures have been taken by the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds a secondary global threshold value, the method includes reducing a queue length for the solid state memory device.

Control of solid state memory device temperature using queue depth management

Processing, such as debug and/or recovery processing, within a communications environment is facilitated. Responsive to detecting an event, a stop signal is propagated through a communications network of the communications environment, and each network element that receives the stop signal, transmits the signal to its neighbors (if any), and then performs an action depending on its specific programming. The action can be to take no action, perform a debugging action or perform a recovery action. The elements that receive the signal and perform the same action as other elements form a coordinated network providing a coordinated result.

Facilitating processing in a communications environment using stop signaling

Fast error reporting is provided in networks that have an architected delayed error reporting capability. Errors are detected and reported without having to wait for a timeout period to expire. Further, failures of other components caused by the delay are avoided, since the delay is bypassed.

Sideband error signaling

A computer program product for integrated key serving is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes using a smart card of two or more smart cards with a support element of two or more support elements to create an encryption key and storing the encryption key in an encrypted file that can only be decrypted by the smart card and the support element used to create the encryption key.

Integrated key server

Initialization of a bidirectional, self-timed parallel interface with capacitive coupling is provided. The self-timed interface includes master and slave nodes connected by a parallel bus comprising multiple AC differential wire pairs. The initialization includes automatically testing at least one wire pair of the multiple AC differential wire pairs for conductivity failure, wherein the testing is responsive to a link reset signal of a first frequency. The automatically testing includes employing a link test signal of a second frequency to test the at least one wire pair of the multiple AC differential wire pairs. The second frequency is a lower frequency than a third, operational signal frequency of the self-timed parallel interface, and the first frequency and the second frequency comprise different frequencies. An initialization testing and handshake approach between the master node and slave node is also provided.

Initialization of a bidirectional, self-timed parallel interface with automatic testing of AC differential wire pairs

The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations. A checksum mechanism is also provided to insure accurate operation without impacting speed and without significantly increasing complexity. While the present disclosure is directed to a complex system which includes a number of features, the present application is particularly directed to circuits and methods for carrying out modular exponentiation.

Circuits and methods for modular exponentiation

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Poughkeepsie, NY, United States of America

Edward W Chencinski