Intel Corporation

Edward V Gamsaragan

Varghese George

Vladimir M Pentkovski

Deep K Buch

Paul M Zagacki

Sanjeev S Jahagirdar

Shay Gueron

Martin Guy Dixon

Jesse R Walker

Ernie F Brickell

Howard C Herbert

Stephen Anthony Fischer

David Johnston

George W Cox

James S Coke

Alberto J Martinez

Charles E Dike

Scott E Siers

Hans Schipper

Guillaume Denneulin

Serge Fabre

Gunendran Thuraisingham

Jose Mendes Carvalho

Greg W Piper

Sylvere Billout

Benoit Renault

An exciter device for transmitting vibration to a support is described. The exciter device comprises a housing, wherein a portion of the housing comprises an interior surface and an exterior surface, the interior surface disposed inside the housing and the exterior surface disposed outside the housing. An exciter is disposed on the interior surface. A rubber suspension is integrated into the portion of the housing. A printed circuit board comprising an amplifier forms a top of the exciter device.

Adaptive signal customization

A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source 'extra' bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource.

Digital random number generator using partially entropic data

A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.

Processor power consumption control and voltage drop via micro-architectural bandwidth throttling

A method of and apparatus for selective delivery of an interrupt to one of multiple processors having independent operating systems is described. The interrupts are generated from various platform devices in the computer system. Depending on the mode of operation of the system, a controller is configured to deliver interrupts to a co-processor when the host processor is off, without turning on the host processor. The interrupt may be delivered to the correct processor using wither a bus-based message or a dedicated interrupt line.

Selective interrupt delivery to multiple processors having independent operating systems

A method of and apparatus for selective delivery of an interrupt to one of multiple processors having independent operating systems is described. The interrupts are generated from various platform devices in the computer system. Depending on the mode of operation of the system, a controller is configured to deliver interrupts to a co-processor when the host processor is off, without turning on the host processor. The interrupt may be delivered to the correct processor using either a bus-based message or a dedicated interrupt line.

A Method and Apparatus for Mapping Address Space of Integrated Programmable Devices within Host System Memory is described herein.

Method and apparatus for mapping address space of integrated programmable devices within host system memory

Growing community of inventors

El Dorado Hills, CA, United States of America

Edward V Gamsaragan