International Business Machines Corporation

Edward Thomas Malley

Fadi Y Busaba

David S Hutton

John G Rell, Jr

Brian Robert Prasky

James J Bonanno

Adam B Collura

Christian Jacobi

Gregory William Alexander

Eric M Schwarz

Anthony Saporito

Brian William Curran

Chung-Lung K Shum

Jonathan D Bradbury

Khary J Alexander

James Raymond Cuffney

Jang-Soo Lee

Jonathan T Hsieh

Jeffrey S Plate

Christopher A Krygowski

Bruce C Giamei

Aaron Tsai

Vimal M Kapadia

Dominic Ditomaso

Michael T Huffer

Timothy John Slegel

Brian David Barrick

Michael J Cadigan, Jr

Wen H Li

Eyal Naor

Lawrence Joseph Powell, Jr

Avraham Ayzenfeld

Yair Fried

Deepankar Bhattacharjee

Richard Joseph Branciforte

Gregory Miaskovsky

Suman Amugothu

Eric Mark Schwarz

A method of branch prediction in a processor includes: obtaining, by the processor, a branch instruction for which a direction of a branch is to be predicted; generating, by the processor, an index based on an instruction address, a global path vector (GPV), and a counter; selecting, by the processor, an entry from a data structure using the index; and predicting, by the processor, the direction of the branch using information included in the selected entry. The method may include modifying a tag in the selected entry based at least in part on another GPV.

Branch prediction using speculative indexing and intraline count

Embodiments for a metadata predictor. An index pipeline generates indices in an index buffer in which the indices are used for reading out a memory device. A prediction cache is populated with metadata of instructions read from the memory device. A prediction pipeline generates a prediction using the metadata of the instructions from the prediction cache, the populating of the prediction cache with the metadata of the instructions being performed asynchronously to the operating of the prediction pipeline.

Metadata predictor

Aspects of the invention include a computer-implemented method of updating metadata prediction tables. The computer-implemented method includes establishing, in the metadata prediction tables, a prediction of how a set of instructions will resolve and identifying that the set of instructions is completed. The computer-implemented method also includes determining, upon completion of the set of instructions, whether prediction update queues (PUQs) associated with the set of instructions indicate that the set of instructions resolved in one of a plurality of prescribed manners relative to the prediction and deciding that the metadata predictions tables are candidates to be updated based on the PUQs indicating that the set of instructions resolved in one of the plurality of prescribed manners.

Updating metadata prediction tables using a reprediction pipeline

Embodiments include storing return addresses for a branch-target-buffer. Aspects include receiving a first instruction and based on a determination that the first instruction is a branch instruction and potentially a call, storing a return address associated with the branch instruction in a prediction return address table, wherein the prediction return address table includes an entry that corresponds to an index value that is created based on a target address of the first instruction, and wherein the entry includes the return address that is created based on an address of a sequential instruction of the first instruction. Aspects also include receiving a second instruction and based on a determination that the second instruction is predicted to be a return instruction with a predicted return address table index value from the branch-target-buffer, using the index value to select the return address to predict as the target address.

Return address table branch predictor

Embodiments are provided for an integrated semi-inclusive hierarchical metadata predictor. A hit in a second-level structure is determined, the hit being associated with a line of metadata in the second-level structure. Responsive to determining that a victim line of metadata in a first-level structure meets at least one condition, the victim line of metadata is stored in the second-level structure. The line of metadata from the second-level structure is stored in a first-level structure to be utilized to facilitate performance of a processor, the line of metadata from the second-level structure including entries for a plurality of instructions.

Integrated semi-inclusive hierarchical metadata predictor

A single architected instruction to produce a signature for a message is obtained. The instruction is executed, and the executing includes determining a sign function of a plurality of sign functions supported by the instruction to be performed. Input for the instruction is obtained, and the input includes a message and a cryptographic key. A signature is produced based on the sign function to be performed and the input. The signature is to be used to verify the message.

Compute digital signature authentication sign instruction

Methods, systems and computer program products for dynamically selecting an OSC hazard avoidance mechanism are provided. Aspects include receiving a load instruction that is associated with an operand store compare (OSC) prediction. The OSC prediction is stored in an entry of an OSC history table (OHT) and includes a multiple dependencies indicator (MDI). Responsive to determining the MDI is in a first state, aspects include applying a first OSC hazard avoidance mechanism in relation to the load instruction. Responsive to determining that the load instruction is dependent on more than one store instruction, aspects include placing the MDI in a second state. The MDI being in the second state provides an indication to apply a second OSC hazard avoidance mechanism in relation to the load instruction.

Dynamic selection of OSC hazard avoidance mechanism

A computer-implemented method for marking load and store instruction overlap in a processor pipeline is described. The method includes detecting a load instruction following a store instruction in an instruction stream. The load instruction and the store instruction include instruction text. The instruction text includes operand address information. The method includes comparing operand address information of the store instruction with operand address information of the load instruction to determine whether there is a memory image overlap in an issue queue between the operand address information of the store instruction and the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to determining that there is a memory image overlap.

Comparing load instruction address fields to store instruction address fields in a table to delay issuing dependent load instructions

A single architected instruction to perform scalar multiplication for cryptographic operations is obtained. The instruction is executed, and the executing includes determining a scalar multiply function of a plurality of scalar multiply functions supported by the instruction to be performed. Input for the scalar multiply function is obtained, and the input includes at least one source component and a scalar value. The scalar multiply function is performed using the input to provide an output to be used in a cryptographic operation.

Perform cryptographic computation scalar multiply instruction

Methods and systems for controlling writing to register files in a processing system having at least two execution pipelines are provided. Aspects include obtaining a micro operation for execution by an execution unit of a first pipeline in the processing system, wherein the micro operation includes writing data to a register file. Aspects also include determining whether the data will be accessed by an execution unit of a second pipeline in the processing system. Based on a determination that the data will only be accessed by the execution unit of the first pipeline, aspects include blocking writing of the data to a register file of the second pipeline.

Write power optimization for hardware employing pipe-based duplicate register files

A computer implemented method for marking a store instruction overlap in a processor pipeline is provided. A non-limiting example of the method includes detecting a second store instruction subsequent to a first store instruction in an instruction stream, in which there is a match between the operand address information of the first store instruction and a load instruction. The operand address information of the first store instruction is compared with the operand address information of the second store instruction to determine whether there is match. In the event of a match, the second store instruction is delayed in the processor pipeline in response to determining that there is a memory image overlap between the operand address information of the second store instruction and the first store instruction.

Store instruction to store instruction dependency

A single architected instruction to verify a signed message is executed. The executing includes determining a verify function of a plurality of verify functions supported by the instruction to be performed and obtaining input for the instruction. The input includes a message and a key. Based on the verify function to be performed and the input, a signature of the message is verified.

Compute digital signature authentication verify instruction

A single architected instruction to produce a signature for a message is executed. The executing includes determining an encrypted sign function of a plurality of encrypted sign functions supported by the instruction to be performed and obtaining input for the instruction. The input includes a message and an encrypted cryptographic key. Based on the encrypted sign function to be performed and the input, a signature to be used to verify the message is produced.

Compute digital signature authentication sign with encrypted key instruction

Provided are embodiments including a computer-implemented method, system and computer program product for determining precise operand-store-compare (OSC) predictions to avoid false dependencies. Some embodiments include detecting an instruction causing an OSC event, wherein the OSC event is at least one of a store-hit-load event or a load-hit-store event, marking an entry in a queue for the instruction based on the detected OSC event, wherein marking the entry comprises setting a bit and saving a tag in the entry in the queue. Some embodiments also include installing an address for the instruction and the tag in the history table responsive to completing the instruction.

Making precise operand-store-compare predictions to avoid false dependencies

Embodiments of the present invention provide a system for balancing a global completion table (GCT) in a microprocessor via frontend steering or stalls. A non-limiting example of the system includes an instruction dispatch unit (IDU) that includes an instruction queue and the system includes an instruction sequencing unit (ISU) that includes a GCT having a first area and a second area. The IDU is configured to determine whether a full group of instructions exist in the instruction queue and to determine whether additional instructions will be received by the instruction queue in a subsequent cycle. The IDU is configured to stall the instruction queue for at least one cycle until a full group of instructions is accumulated at the instruction queue upon determining that additional instructions will be received by the instruction queue in subsequent cycle.

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New Rochelle, NY, United States of America

Edward Thomas Malley