Intel Corporation

Intel Corporatoin

Tahoe Research, Ltd.

Edward Thomas Grochowski

Robert Valentine

Mark Jay Charney

Dennis Ryan Bradford

Hong Wang

John H Crawford

Asit K Mishra

Jesus Corbal

Milind Baburao Girkar

Elmoustapha Ould-Ahmed-Vall

Andrew Thomas Forsyth

Bret L Toll

Thomas D Fletcher

Nhon Toai Quach

John P Shen

James Paul Held

Deborah T Marr

Perry H Wang

Jesus Corbal San Adrian

Robert Dale Cavin

Ralph Michael Kling

Vinod Sharma

Partha Kundu

Jonathan D Pearce

Jamison D Collins

Tin-Fook Ngai

Hans J Mulder

Simon C Steely, Jr

Donald B Alpert

Jonathan Cannon Hall

Suleyman Sair

Seth Abraham

Charles R Yount

Gilbert A Neiger

Ian A Young

Christopher J Hughes

Rajesh M Sankaran

Eriko Nurvitadhi

David J Sager

Koichi Yamada

John Thomas Shen

Joseph Nuzman

Stephen R Van Doren

George Zacharias Chrysos

Paul Caprioli

Lokpraveen B Mosur

Narayan Ranganathan

Kent D Glossop

Niall D McDonnell

Richard J Greco

Jeffrey J Cook

Ganesh Venkatesh

Jason W Brandt

Stephen H Gunther

Shih-Lien L Lu

Victor W Lee

David B Papworth

Derrick Chu Lin

Robert S Chappell

Kenneth D Shoemaker

Bryan P Black

Thomas R Huff

Roger Gramunt

James D Allen

Stefan Rusu

Baiju V Patel

Per H Hammarlund

Scott Dion Rodgers

Prashant Sethi

Gautham N Chinya

Hang T Nguyen

Shivnandan D Kaushik

Bryant E Bigbee

Xiang Chris Zou

Lihu Rappoport

Richard A Hankins

Eric A Sprangle

Daehyun Kim

Naveen K Mellempudi

Ronak Singhal

Xinmin Tian

Sheng C Li

Ehud Cohen

Doron Orenstein

Joshua B Fryman

Michael D Upton

James Steven Burns

Federico Ardanaz

Martin Guy Dixon

Michael E Kounavis

Gad Shlomo Sheaffer

Ronny Ronen

Christopher B Wilkerson

Peter D MacWilliams

Ravi Rajwar

Samson X Huang

Gregory Scott Mathews

Douglas M Carmean

Michael Behar

Jared Warner Stark, Iv

A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.

Interruptible and restartable matrix multiplication instructions, processors, methods, and systems

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Systems, methods, and apparatuses for heterogeneous computing

Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

Apparatuses and methods for a processor architecture

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Vector friendly instruction format and execution thereof

Embodiments of systems, apparatuses, and methods for chained fused multiply add. In some embodiments, an apparatus includes a decoder to decode a single instruction having an opcode, a destination field representing a destination operand, a first source field representing a plurality of packed data source operands of a first type that have packed data elements of a first size, a second source field representing a plurality of packed data source operands that have packed data elements of a second size, and a field for a memory location that stores a scalar value. A register file having a plurality of packed data registers includes registers for the plurality of packed data source operands that have packed data elements of a first size, the source operands that have packed data elements of a second size, and the destination operand. Execution circuitry executes the decoded single instruction to perform iterations of packed fused multiply accumulate operations by multiplying packed data elements of the sources of the first type by sub-elements of the scalar value, and adding results of these multiplications to an initial value in a first iteration and a result from a previous iteration in subsequent iterations.

Systems, apparatuses, and methods for chained fused multiply add

A processor includes a decode unit to decode an instruction that is to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, and to indicate one or more destination storage locations. The execution unit, in response to the instruction, is to store at least one result mask operand in the destination storage location(s). The at least one result mask operand is to include a different mask element for each corresponding data element in one of the first and second source packed data operands in a same relative position. Each mask element is to indicate whether the corresponding data element in said one of the source packed data operands equals any of the data elements in the other of the source packed data operands.

Data element comparison processors, methods, systems, and instructions

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San Jose, CA, United States of America

Edward Thomas Grochowski