Eastman-kodak Company

Truesense Imaging, Inc.

International Business Machines Corporation

Semiconductor Components Industries, LLC

Omnivision Technologies, Inc.

United States of America As Represented by the Secretary of the Air Force

Truesence Imaging, Inc.

Edward T Nelson

Shen Wang

Eric Gordon Stevens

Charles V Stancampiano

John J Ellis-Monaghan

James William Adkisson

Mark David Jaffe

John Thomas Compton

Richard John Rassel

James P Lavine

R Michael Guidash

Gilbert Allan Hawkins

Timothy John Tredwell

Robert Michael Guidash

David L Losee

David N Nichols

David Michael Boisvert

Herbert J Erhardt

Eric J Meisenzahl

Edmund Kenneth Banghart

Bruce C Burkey

John P Shepherd

William F DesJardin

R Daniel McGrath

Christopher R Hoople

In various embodiments, a time-delay-and-integrate (TDI) image sensor includes (i) a plurality of integrating CCDs (ICCDs), arranged in parallel, that accumulate photocharge in response to exposure to light, (ii) electrically coupled to the plurality of ICCDs, a readout CCD (RCCD) for receiving photocharge from the plurality of ICCDs, and (iii) electrically coupled to the RCCD, readout circuitry for converting charge received from the RCCD into voltage.

Time-delay-and-integrate image sensors having variable intergration times

An integrated circuit includes a device identification circuit and a temperature sensor diode connected in parallel from a common node. The device identification circuit includes a resistor connected to a diode-connected transistor. The device identification circuit and the temperature sensor diode are adapted to not be simultaneously operating in an ON state. A first voltage is applied to the common node to place the device identification circuit in an ON state and place the temperature sensor diode in an OFF state to identify the integrated circuit. A second voltage is applied to the common node to place the device identification circuit in an OFF state and place the temperature sensor diode in an ON state to determine a temperature of the integrated circuit.

Device identification and temperature sensor circuit

In various embodiments, image sensors include photosensitive pixels, associated vertical CCDs, sense nodes each accepting charge from one or more of the vertical CCDs, and readout circuitry accepting signals from the sense nodes.

CCD image sensors and methods

Time-delay-and-integrate image sensors having variable integration times

A Charge-Coupled Device (CCD) image sensor includes a linear array of photodetectors. The photodetectors in the linear array are arranged into distinct sub-arrays with each sub-array including two or more photodetectors. An output channel is connected to each sub-array of photodetectors. Each output channel includes a horizontal CCD shift register and an output structure connected to an end of the horizontal CCD shift register in a linear arrangement with respect to each other. Each successive output channel is disposed on an alternate side of the linear array. Every other output channel is disposed on an alternate side of the linear array. One or more dark reference pixels can be connected to one or more additional shift register elements in the horizontal CCD shift registers.

Method for producing a linear image sensor having multiple outputs

Linear image sensor with multiple outputs

A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.

Methods of forming silicide strapping in imager transfer gate device

A method for lowering dark current in an image sensor pixel, the method includes the steps of providing a photosensitive area for receiving incident light which is converted into a charge; providing a gate for transferring charge from the photosensitive area; wherein the gate is held at a voltage which will accumulate majority carriers at a semiconductor-dielectric interface during integration for the photosensitive area. Alternatively, a potential profile can be provided under the gate to drain the dark current away from the photogeneration diffusion.

Camera, image sensor, and method for decreasing undesirable dark current

Silicide strapping in imager transfer gate device

A method for calibrating an image sensor having multiple outputs, the method includes the steps of capturing an image on the image sensor, injecting one or more substantially identical pairs of signals into corresponding portions of the captured image, reading out the captured image with the injected signals into two or more outputs, and comparing two substantially identical signals from corresponding portions of the image, which comparison is used for calibrating the image.

On-chip block balancing structure and method for multiple output image sensors

A charge-coupled device having an improved charge-transfer efficiency over a broad temperature range. The device comprises a substrate of semiconductor material of one conductivity type; a first buried channel formed in the substrate and of a conductivity type opposite to that of the substrate; a second buried channel of a conductivity type opposite to that of the substrate formed in the same region of the substrate as the first buried channel and having a greater depth of penetration into the substrate than the first buried channel; compensated regions formed at intervals in the buried channels providing a means for containing individual packets of charge and shaped for inducing a narrow channel effect and for producing a fringing electric field in a direction of charge transfer in uncompensated buried channel regions; electrode gates associated with each pair of adjoining compensated and uncompensated regions in the device; and means for clocking the electrodes for causing a string of charge packets to be transferred through the device.

Charge-coupled device having an improved charge-transfer efficiency over

A charge coupled device having a layer of a semiconductor material on a surface of a substrate body of a semiconductor material. The layer is of a material which can be epitaxially deposited on the body with good crystalline quality. The material of the layer has a conduction band and/or valence band which is different from that of the body so as to provide a discontinuity in the energy level of the conduction band and/or valence band at the junction of the layer and the body during the operation of the charge coupled device. At least one electrode is over and insulated from the layer. The discontinuity in the conduction band and/or valence band creates a well in which photogenerated charge is collected.

Charge coupled device (CCD) having high transfer efficiency at low

An interline transfer type area image sensor which operates in a non-interlaced mode and has an array of columns and rows of photoreceptor in which charge from each pixel is transferred into a stage of a vertical two-phase CCD shift register formed by adjacent electrodes of the CCD. Each electrode of a stage has a separate voltage clock. An ion implanted vertical transfer barrier region is formed under an edge of each electrode.

Non-interlaced interline transfer CCD image sensing device with

A high-gain, low-noise transistor amplifier comprises an input, an output, and first and second field effect transistors each having a gate, a drain, and a source and being formed in a common semiconductor substrate. The second transistor is a depletion mode transistor if it is of the same conductivity type as the first but is an enhancement mode transistor if it is of opposite conductivity type with respect to the first. In an amplifier configuration, the input is coupled to the gate of the first transistor, the source of the first transistor is coupled to the gate of the second transistor, the source of the second transistor is coupled to the output, and there is a direct-coupled feedback path from the source of the second transistor to the drain of the first transistor. At least the first transistor is formed in an isolated well of conductivity opposite to that of the substrate in the semiconductor substrate and its source is coupled directly to that well.

High-sensitivity, low-noise transistor amplifier

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Pittsford, NY, United States of America

Edward T Nelson