Raytheon Company

Delaware Corporation

Edward T Lewis

Moshe Mazin

Dale L Montrone

Jun-ichi Sano

William A Sciarretta

Simon Bessendorf

Dennis A Henlin

Richard V Kemper

James E Meister

M Halberstam

The invention provides apparatus and methods for detecting electromagnetic energy using an array of detectors arranged in at least one row and multiple columns. A single crystal body has multiple doped regions disposed therein. Each one of the detectors produces charge in a corresponding one of the doped regions in the body in response to electromagnetic energy impinging upon that detector. A first charge transfer device includes an output port and multiple serially coupled charge storage cells including multiple first charge transfer regions disposed in the body parallel to the row, or rows, of detectors. Multiple second charge transfer devices include multiple second charge transfer regions disposed in the body transverse to the row, or rows, of detectors and the charge storage cells. Each one of the second charge transfer regions is adapted to transfer charge produced in a corresponding one of the doped regions to a corresponding one of the charge storage cells. Each one of the doped regions corresponding to one of the detectors has a doping profile adapted to produce an electric field in a direction from the doped region toward a corresponding one of the multiple second charge transfer regions. Such an arrangement allows dual polarization detection with little or no modification of the system configuration.

Electromagnetic energy detection

Bias networks for producing a predetermined bias current for another circuit are provided. The bias networks include compensation subcircuits which provide compensation for process variations in the transistors in the network. Circuit implementations which allow for compensation for power supply voltage variations are also provided. The bias networks include a biasing transistor and a corresponding compensation transistor on the same chip which compensation transistor will have substantially the same process variations as the biasing transistor. The compensation transistor is interposed at a node in a control path and draws current at the node such that a change in the current drawn by the compensation transistor causes a change in the input voltage of the biasing transistor to thereby adjust the bias current produced by the transistor to maintain the bias current within design specifications despite process variations. Bias circuit configurations for a cascode amplifier, a differential amplifier, and a current mirror are provided.

Bias circuit having process variation compensation and power supply

A content limit addressable memory (CLAM) having a plurality of lower and upper limits stored therein for comparison to corresponding subfields of an input word. Each corresponding upper and lower limit forms a bracket. Corresponding brackets form a window. The brackets correspond to the subfields and are of the same number of bits. The brackets and subfields are alterable in width to allow each bracket and subfield to have any number of bits in multiples of two. A valid match of the input word with any window can occur with any combination of the brackets of a window matching or not matching the corresponding subfields of the input word. A plurality of outputs corresponding to each of the windows indicates a match of the corresponding window to the input word. Additionally, the CLAM can compare data stored therein against an applied window with the matching operations as described above.

Content limit addressable memory

Mode programmable VLSI CMOS data registers perform on-chip self-test. A first data register performs storage or transfer of data, operates in a scan mode or generates pseudo-random numbers (PRN). A second data register performs storage or transfer of data, operates in a scan mode or performs signature analysis. Data initialization of the registers occurs automatically when operating in a test mode.

Mode programmable VLSI data registers

An interface circuit for converting a differential input voltage, having a common-mode level within a first range, into a differential output voltage having a different, common-mode level. The circuit feeds current between a pair of variable current sources and a pair of input terminals adapted to receive the differential input voltage through a pair of resistors. The amount of current passing through the pair of resistors is related to the common-mode level of the input signal. The resistors produce the differential output voltage at the pair of output terminals with a common-mode level related to the common-mode level of the input voltage translated an amount related to the amount of current passing through them.

Interface circuit having differential signal common mode shifting means

A semiconductor device referred to as complementary metal electrode semiconductor (CMES) has p-type and n-type silicon MESFETs interconnected on a substrate with an n-type barrier enhancement implanted into the p-channel of the p-type MESFET. The structure and method of fabrication are provided for forming a CMES logic inverter which has characteristics of very low power, low voltage, low noise and high speed.

Method of making a complementary metal electrode semiconductor device

Complementary metal electrode semiconductor device

A high speed full adder circuit is shown to include logic circuitry responsive to the levels of the two digital signals to be added for: (a) immediately producing an appropriate carry signal when the levels of the digital signals are the same; and (b) inverting the carry signal into such adder when the levels of the digital signals differ.

High speed full adder

A high speed CMOS binary up/down counter having a 200 MHZ clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. The counter performs in an up-count mode or a down-count mode in accordance with the state of a mode select signal. Each stage of the 4-bit counting section comprises a propagate/kill/generate gate for determining the status of a carry signal to a next stage, except the last stage of a 4-bit section, which does not require such a gate because it is coupled to a carry-forward generator along with the outputs from the other preceeding stages in the section. Each 4-bit section performs the counting function through a successive process of modulo-two sums of a lower order carry and the current state of a counter stage without the need for cumbersome gating structures.

CMOS binary up/down counter

A variable field content addressable memory (VFCAM) unit cell comprises a 4-bit content addressable memory, a programmer and a field selector. A limited capability of comparing between limits is provided by using mask bits at the data line inputs to the VFCAM unit cell. A plurality of VFCAM unit cells may be cascaded vertically and horizontally to provide a Y words by X bits VFCAM array. The VFCAM array is programmable by a field code coupled to field partition logic which selects the same number of fields in all memory locations and the number of bits in each field, and an operational VFCAM system results when the VFCAM array is coupled to an input address decoder, an I/O register and an output encoder.

Variable field content addressable memory

A CMOS output driver having precise control of rise and fall times of signals generated from the output driver on a VLSI semiconductor chip. Two time-dependent voltage generators provide a separate ramp signal to each one of the gates of a CMOS inverter circuit. The ramp signal characteristics of each voltage generator are determined by the combination of a controlled current source charging a known capacitance.

CMOS VLSI output driver with controlled rise and fall times

A 1.2 .mu.m CMOS binary counter having a 200 MHz clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. Each bit stage within a 4-bit counter section uses the current state of such stage to determine what happens in the next stage. Each 4-bit section performs the counting function through a successive process of additions of a lowest order carry-bit input. A count enable signal serves to enable the count process as well as serving as a carry-bit input to a first stage. Count enable effects a counter reset when in a logic 'zero' state. Once the count enable is raised to the logic 'one' state, the process of counting begins with the rising edge of the first clock pulse. As long as the count enable is maintained, counting continues. When the count enable is reduced to a 'zero' state, counting is terminated, with a counter reset occurring on the next sequential rising edge of the clock.

CMOS binary counter

Unified CMOS logic circuits are based on a structured implementation of transmission-gates. The basic logic building blocks for AND and OR circuits comprise a plurality of transmission-gates some of which may be simplified to a reduced form of a single pass transistor resulting in fewer transistors for implementing logic functions without loss of logic circuit performance characteristics. Three variable logic functions and higher order logic functions are easily implemented. Generally, the required VLSI chip area is minimized as a result of this structured transmission-gate approach.

Transmission-gate structured logic circuits

An adder/subtractor wherein N/2 two bit adders are connected to allow the addition of numbers having N bits, each one of the two bit adders having associated control circuitry adapted: (a) to cause each two bit adder either to add applied bits directly or to add one applied bit and the 'two's complement' of the other bit; and (b) to electrically separate any selected ones of the two bit adders from the others.

Growing community of inventors

Sudbury, MA, United States of America

Edward T Lewis