International Business Machines Corporation

Edward T Gerchman

Randall Scott Jensen

Mark C Gildea

Warren Edward Maule

Michael F Fee

William Paul Hovis

Ekaterina M Ambroladze

Andrew Henry Wottreng

Arthur J O'Neill, Jr

Thomas James Osten

Dynamic pipeline cache error correction includes receiving a request to perform an operation that requires a storage cache slot, the storage cache slot residing in a cache. The dynamic pipeline cache error correction also includes accessing the storage cache slot, determining a cache hit for the storage cache slot, identifying and correcting any correctable soft errors associated with the storage cache slot. The dynamic cache error correction further includes updating the cache with results of corrected data.

Dynamic pipeline cache error correction

A memory controller, upon detecting an interval of inactivity (that is, no read or write access from a processor or I/O devices with respect to main storage or memory SDRAMs) halts external refresh commands from the processor, and initiates STR mode in main storage to preserve data contents in the memory SDRAMs and to save energy. Then, upon detecting a read or write operation, the memory controller signals main storage to exit STR mode.

System and method for memory self-timed refresh for reduced power consumption

A storage controller, upon detecting an interval of storage inactivity, inhibits external storage refresh commands and places the storage in self timed refresh (STR) mode. Upon detecting storage activity while storage is in STR mode, the controller terminates STR mode in storage. Upon detecting a scrub request while storage is in STR mode, the controller terminates STR mode in the storage and thereafter services the scrub request. Upon completing execution of the scrub request, the controller returns storage to STR mode.

System and method for memory scrub during self timed refresh

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Endwell, NY, United States of America

Edward T Gerchman