Motorola Corporation

Edward T Clark

Enrique Ferrer

Paul H Gailus

William J Turney

William J Martin

Terry K Mansfield

Joshua E Dorevitch

An integrated sigma-delta radio frequency (RF) receiver subsystem ( ) and method utilizes a multi-mode sigma-delta analog-to-digital converter ( ) for providing a single and multi-bit output. A programmable decimation network ( ) for reducing the frequency of the in-phase and quadrature bit stream and a programmable formatting network ( ) are also used for organizing the in-phase and quadrature components from the decimation network ( ) for subsequent signal processing. The invention offers a highly integrated digital/analog RF receiver back-end which incorporates integrated filtering and a smart gain control that is compatible for use with other receiver systems and offering superior performance characteristics.

Integrated multi-mode bandpass sigma-delta receiver subsystem with interference mitigation and method of using same

An integrated multi-mode bandpass sigma-delta radio frequency receiver subsystem with interference mitigation includes a first intermediate frequency amplifier. At least one mixer for mixing the output of the first amplifier and an oscillator signal. A second IF amplifier for amplifying and filtering the output of the at least one mixer. A multi mode multi bandwidth sigma delta analog digital converter for providing digital output signals with high dynamic range. A digital mixer providing I and Q signals a decimation network providing I and Q signals at reduced programmable data and clock frequencies and a formatting network for arranging the I and Q signals into a predetermined format for use with a digital signal processor.

Integrated multi-mode bandpass sigma-delta receiver subsystem with

A voltage multiplier rectifier filter circuit comprising capacitors C3 and C4 and diodes D1 and D3 multiples, rectifies and filters the voltage at an input terminal (T1) of the switch. A diode (D2) is connected to the output of the multiplier-rectifier-filter circuit to provide a lesser bias voltage in the absence of a signal at the input terminal (T1). Four transistors (Q1-Q4) switch this bias voltage ON and OFF to the gates of four GaAs transistors (S1-S4). The GaAs transistors selectively couple signals between the input and output signal terminals (T1-T4) of the switch.

Gallium arsenide antenna switch having voltage multiplier bias circuit

A transceiver determines the signal quality of a desired signal and the strength of all received signals. When the signal quality of the desired signal is low, and the signal strength of all received signals is high, the receiver is adapted to operate in a higher current mode, thereby minimizing intermodulation distortion. Conversely, when the quality of the desired signal is low and the strength of all received signals is also low, or when the quality of the desired signal is above a threshold, the receiver operates in a lower current mode to conserve power and maximize battery lifetime. Also, when the transceiver adapts to operate in the higher current mode, a command is sent instructing a transmitting party to increase the quality of their message which may enable the listening transceiver to adapt (return) to a lower current mode.

Communication system with adaptive transceivers to control

An electronic switch uses GaAs transistors to switch signals that have peak-to-peak voltage swings that exceed the breakdown voltage of the transistors. A two port impedance transformer (Z1) has a high input impedance and a low output impedance to transform a high voltage input signal (at T1) to a corresponding output signal having lower voltage, but higher current. This transformed signal is coupled to the second port of a three port impedance transformer (Z2) through a first GaAs transistor switch (Q1). A half wave rectifier circuit (D1, R7, R8 and C3) generates a negative DC voltage from the input signal (at T1), thereby eliminating the requirement for a separate bias voltage supply. A bipolar transistor switch selectively couples this negative bias voltage to the gate of the first GaAs transistor (Q1). The second port of the three port impedance transformer (Z2) has a lower impedance than either the first or third ports. A second GaAs transistor switch (Q2) is coupled between the third port of the three port impedance transformer (Z2) and ground, and a third GaAs transistor switch (Q3) couples the third port to a output terminal (T6) of the switch. The first port of the three port impedance transformer (Z2) is coupled to an input/output terminal (T2) of the switch.

Gallium arsenide antenna switch

An RF signal is transformed (12 and 12') to increase its current component, while reducing its voltage component below the voltage that would damage a GaAs switching device (16 or 16'). The current and voltage transformation are selected so that the power of the RF signal remains substantially constant. Subsequent to the GaAs switching device, the signal is converted (24 and 24') to increase the voltage component while decreasing its current component to substantially recreate the original RF signal.

Growing community of inventors

Plantation, FL, United States of America

Edward T Clark