International Business Machines Corporation

Edward Seewann

Terry I Chappell

Rudolf Adriaan Haring

Sang Hoo Dhong

Bruce Martin Fleischer

Barbara A Chappell

Michael Kevin Ciraula

Mark S Milshtein

Talal K Jaber

Michael P Beakes

Talal Kamel Jaber

Max Eduardo De Ycaza

Pho Hoang Nguyen

A high performance register that can be used as a pipelined register in logic chips that are designed using a pulsed logic methodology is described. The register features minimal setup time, pulse catching and pulse launching. The register circuitry complies with and implements a circuit-level test methodology for pulsed logic that features the ability to inhibit the reset of pulses, to force resets and to operate the circuits in a pseudo static mode. The register also complies with the level sensitive scan design (LSSD) methodology. Also described is a state-holding static master-slave register that complies with a pulsed logic design methodology, the register exhibiting an automatic power reduction feature and a simplified modular register bit design which can easily be adapted to either static domino or pulsed logic. The register is also LSSD compliant. Also described is the means and method for allowing static transmission gate input registers to comply with the static evaluate test mode. The automatic power reduction feature can be extended to downstream logic.

High performance registers for pulsed logic

A pulsed logic circuit test methodology and circuitry therefor are disclosed. The methodology and circuitry allow the inhibiting of reset pulses, the ability to force resets and the ability to test the circuit in a pseudo-static mode of operation.

Methodology to test pulsed logic circuits in pseudo-static mode

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Austin, TX, United States of America

Edward Seewann