International Business Machines Corporation

Edward Scott Kirkpatrick

Christos J Georgiou

Thor A Larsen

Chandrasekhar Narayanaswami

Robert K Montoye

Winfried W Wilcke

Ralph Linsker

Lurng-Kuo Liu

Frederik C M Kjeldsen

Eric P Kronstadt

Charles D Gelatt, Jr

John F Cooper

An image capturing system and method for automatically watermarking a plurality of recorded camera and image parameters such as the location (latitude, longitude and altitude), orientation of the principal axis of the camera, whether the camera is in landscape mode or portrait mode, camera velocity, photographer information, time and date, zoom factor, shutter speed, flash on/off, autofocus distance, lightmeter reading, focal length and aperture into every captured image. This watermarked data can be subsequently extracted and compared with the originally recorded data so as to verify the authenticity of a corresponding image. Since the critical data is invisibly watermarked into the image, it is difficult to modify the image without affecting the watermarked data.

Image capturing system and method for automatically watermarking recorded parameters for providing digital image verification

A method and apparatus are provided for training a computer system to recognize specific actions of a user. This may include displaying an image of a user within a window on a screen. The window includes a target area. This may also include associating a first computer event with a first user action displayed in the target area and storing information in a memory device such that the first user action is associated with the first computer event.

Apparatus and method for using a target based computer vision system for user interaction

System and methods for querying digital image archives containing digital photographs and/or videos (collectively, &ldquo;digital images&rdquo;). The digital images are indexed in accordance with a plurality of recorded parameters including time, date and geographic location data (altitude and longitude), as well as image data such as lens focal length, auto focus distance, shutter speed, exposure duration, aperture setting, frame number, image quality, flash status and light meter readings, which are used for searching a database consisting of the digital images. These images are preferably generated by an image capturing system which is capable of measuring and recording a plurality of parameters with each captured digital image. The image retrieval system allows a querying user to search the image archive by formulating one or more of a plurality of query types which are based on the recorded parameters, and then retrieve and display those images having the specified parameters.

System and methods for querying digital image archives using recorded parameters

A system and method using thermal feedback to cooperatively vary a voltage and frequency of a circuit to control heating while maintaining synchronization. Preferably, on-chip thermal sensors are used for feedback. A system having features of the invention includes: a thermal sensor coupled to the circuit, the thermal sensor generating a temperature signal which is a function of a temperature associated with the functional unit; a temperature decoder having an input and an output, the input coupled to the thermal sensor for decoding the temperature signal; a comparator having one input coupled to the decoder for comparing a decoded temperature signal with a predetermined temperature threshold signal coupled to a second input, the comparator enabling a voltage/clock control signal as a function of the decoded temperature signal and the predetermined temperature threshold; an adjustable voltage regulator coupled to the voltage/clock control signal; and a clock selector coupled to the voltage/clock control signal; wherein the voltage regulator and the clock selector are adapted to cooperatively vary the voltage and the frequency of the circuit to a predetermined voltage-frequency pair, responsive to the voltage/clock control signal.

Performance-temperature optimization by cooperatively varying the

A system and method using thermal feedback to cooperatively vary a voltage and frequency of a circuit to control heating while maintaining synchronization. Preferably, on-chip thermal sensors are used for feedback. A system having features of the invention includes: a thermal sensor coupled to the circuit, the thermal sensor generating a temperature signal which is a function of a temperature associated with the functional unit; a temperature decoder having an input and an output, the input coupled to the thermal sensor for decoding the temperature signal; a comparator having one input coupled to the decoder for comparing a decoded temperature signal with a predetermined temperature threshold signal coupled to a second input, the comparator enabling a voltage/clock control signal as a function of the decoded temperature signal and the predetermined temperature threshold; an adjustable voltage regulator coupled to the voltage/clock control signal; and a clock selector coupled to the voltage/clock control signal; wherein the voltage regulator and the clock selector are adapted to cooperatively vary the voltage and the frequency of the circuit to a predetermined voltage-frequency pair, responsive to the voltage/clock control signal and switching factor means, coupled to the comparator, for varying the switching factor of the circuit, wherein the switching factor is the fraction of clock cycles that the circuit is dissipating power.

A system and method for modulating the switching factor of a circuit to control heating and which does not require modulation of the circuit's clock frequency. The switching factor refers to the fact that due to gating requirements, latency and data transfer characteristics, the rate at which a circuit's inputs are addressed is some fraction of the circuit clock frequency. Application can be made to many existing systems which incorporate single or multiple VLSI circuits such as superscalar microprocessors, parallel processors, DSPs, microcontrollers and MPEG decoders. A method for controlling a switching factor of a multi-functional unit processor includes the steps of: scheduling instructions stored in a memory for execution on each functional unit; generating a first temperature signal for a first functional unit and a second temperature signal for a second functional unit, each temperature signal being a function of a temperature associated with each functional unit; identifying the first functional unit and the second functional unit associated with each temperature signal, responsive to the generating step; comparing the first temperature signal with a first predetermined temperature threshold signal; generating a first temperature delay signal when the first temperature signal exceeds the first predetermined threshold, responsive to the comparison; and reducing the switching factor of the first functional unit according to the first temperature delay signal by delaying scheduling instructions for execution on the first functional unit. Further reduction in power dissipation may be achieved by using thermal feedback to cooperatively vary the voltage and frequency of a circuit.

Performance-temperature optimization by modulating the switching factor

A system and method for optimizing power consumption by a disk drive unit. The system and method monitor and analyze historical use data and calculate a predicted inactivity duration. The predicted inactivity duration is used to power-down the rotational speed of the drive to the first of one or more intermediate rotational speeds. Continued inactivity will result in further speed reduction until the drive is ultimately powered off. The drive increases rotational speed on demand.

Disk drive power management system and method

A method for distributing wire load among the layers of a multilayer interconnection package such that in each region of the package, the wire load is balanced among all layers and such that specified subsets of two-pin connections may be constrained to lie within the same layer.

Method for distributing wire load in a multilayer package and the

An improved testing and checking circuit for a Differential Cascode Voltage Switch which uses N-devices for both the invalid (0,0) and (1,1) state detection of Q and Q switch signals, and uses decoupling pass devices for sampling the data at the fall of the system C-clock, additionally allowing simultaneous pre-charging and error detection. The testing and checking circuit is incorporated in a hierarchical scheme, which uses the system C-clock for input to the latches, decoupling of the buffers, and pulling up and down the error lines. The error fault is held in a system latch. Also described is a circuit scheme which self tests a large macro using only the C-clock and latches the result in a single latch. More particularly, the described circuit employs the Q and Q signals in a NOR configuration, thus detecting if neither signal has sufficient voltage to pull down the load device which consists of a P-device whose gate is attached to the C-clock. The resulting signal is run to a gate in parallel with the two N-devices. Thus, the two low signals allow this NOR gate to rise and produce a pulldown leg to an error line. An invalid signal condition is detected if either both signals are sufficiently high to turn on an N-device or neither signal is high enough to turn on an N-device. Therefore, the described circuit registers a failure if and only if there is the potential for a tree with the same inputs to enter an invalid state.

Test circuit for differential cascode voltage switch

The overall arrangement of a large number of discrete objects may be optimized with relation to the function of or the space occupied by the arrangement by establishing a suitability measure, or score, for each configuration of the arrangement, in relation to the function of or volume occupied, generating random local changes in the arrangement, scoring the effect of the individual changes and subjecting all objects in the arrangement to a random series of incremental changes whose outcome is on average predictable. The procedure lends itself to computer simulation. It may be applied to sequencing and scheduling problems, bin packing types of problems and in complex design problems such as semiconductor chip placement, wiring network routing and logic partitioning.

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Croton-on-Hudson, NY, United States of America

Edward Scott Kirkpatrick