Intel Corporation

Edward S Zager

Gregory Scott Mathews

James P Kardach

Sung Soo Cho

Cau L Nguyen

Kameswaran Sivamani

David S Vannier

Shing Wong

Sundari S Mitra

A cache controller is intimately associated with a microprocessor CPU on a single chip. The physical address bus is routed directly from the CPU to the cache controller where it is sent to the cache tag directory table. For a cache hit, the cache address is remapped to the proper cache set address. For a cache miss, the cache address is remapped in accordance with the LRU logic to direct the cache write to the least recently used set. The cache is thereby functionally divided into associative sets, but without the need to physically divide the cache into independent banks of SRAM.

Single bank associative cache

A cache controller is associated with a microprocessor CPU on a single chip. The physical address bus is routed directly from the CPU to the cache controller where addresses are compared with entries in the cache tag directory table. For a cache hit, the cache address is remapped to the proper cache set address. For a cache miss, the cache address is remapped in accordance with the LRU logic to direct the cache write to the least recently used set. The cache is thereby functionally divided into associative sets, but without the need to physically divide the cache into independent banks of SRAM.

Computer system having a set associative cache memory with sequentially accessed on-chip address tag array and off-chip data array

A variable frequency clock generator provides complementary phase clock signals for a microprocessor at a selectable one of a plurality of frequencies. The outputs may be dynamically switched between any of the frequencies so that every cycle of the phase clock signals has a duration at least as great as the cycle duration of the highest frequency.

An apparatus for providing a clock signal for a microprocessor at a

A cache memory hierarchy having a first level write through cache memory and a second level write back cache memory is provided to a computer system having a CPU, a main memory, and a number of DMA devices. The first level write through cache memory responds to read and write accesses by the CPU, and snoop accesses by the DMA devices, whereas the second level write back cache memory responds to read and write accesses by the CPU as well as the DMA devices. Additionally, the first level write through cache memory is a relatively large cache memory designed to provide a high cache hit rate, whereas the second level write back cache memory is a relatively small cache memory designed to reduce accesses to the main memory. Furthermore, the first level write through cache memory reallocates its cache lines in response to CPU read misses only, whereas the second level write through cache memory reallocates its cache lines in response to CPU write misses only.

Cache memory hierarchy having a large write through first level that

A transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of a microprocessor CPU chip. Upon assertion of this interrupt, the CPU begins program execution in a dedicated RAM area that is inaccessible both to the operating system and all application programs. A set of instructions, which may be unique to the system in which the CPU chip is installed, services the interrupt. Typically, the state of the CPU and associated components in the system immediately prior to assertion of the interrupt will be saved into the dedicated RAM area by the interrupt service routine. Recovery from the interrupt is accomplished upon recognition of an external event that invokes a RESUME instruction causing the CPU and associated components to be restored to exactly the same state that existed prior to the interrupt and in a manner entirely transparent to any program executing at the time of the interrupt.

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San Jose, CA, United States of America

Edward S Zager