Xilinx, Inc.

Xlnx, Inc.

Edward S Peterson

Jason J Moore

James D Wesselkamper

Steven E McNeil

Roger D Flateau, Jr

James B Anderson

Stephen M Trimberger

Boon Yong Ang

Carl H Carmichael

Lawrence C Hung

Lester S Sanders

Brendan K Bridgford

Yatharth K Kochar

Krishna C Patakamuri

Ramakrishna G Poolla

Danny Tsung-Heng Wu

Trevor W Hardcastle

John C Hoffman

A system includes a plurality of watchdog components. Each watchdog component is configured to receive a kick signal from its monitored function to determine whether the monitored function is active. Each watchdog component is further configured to receive a respective token from all watchdog components that the each watchdog component is connected to. The respective token determines whether its respective watchdog component has timed out. Each watchdog component is further configured to generate a token responsive to the kick signal and further responsive to the respective token from all watchdog component that the each watchdog component is connected to. Each watchdog component is further configured to transmit the generated token to the all watchdog components that the each watchdog component is connected to.

Distributed watchdog timer and active token exchange

An array of non-volatile memory cells includes rows and columns. A volatile storage circuit provides addressable units of storage. A control circuit reads first type data and second type data from one or more of the rows and multiple ones of the columns of the array of non-volatile memory cells. The control circuit stores the first type data and second type data read from each row in one or more addressable units of storage of the volatile storage. A security circuit reads first data from the one or more of the addressable units of the volatile storage and selects from the first data, the second type data that includes one or more bits of each of the one or more of the addressable units. The security circuit performs an integrity check on the selected second type data, and generates an alert signal that indicates a security violation in response to failure of the integrity check.

Mixed storage of data fields

Disclosed approaches for controlling debug access to an integrated circuit (IC) device include receiving a debug packet by a debug interface circuit of the IC device. The debug interface circuit authenticates the debug packet in response to the debug packet having a command code that specifies enable debug mode or a command code that specifies disable debug mode. In response to the debug packet passing authentication and the command code specifying enable, the debug interface circuit enables debug mode of the IC device. In response to the debug packet passing authentication and the command code specifying disable, the debug interface circuit disables the debug mode of the IC device. In response to the debug packet failing authentication, the debug interface circuit rejects the debug packet.

System-on-chip having secure debug mode

A disclosed circuit arrangement includes a bank of efuse cells, first and second sense amplifiers coupled to input signals representing constant logic-1 and logic-0 values, respectively, a storage circuit, an efuse control circuit, and an efuse security circuit. The efuse control circuit inputs signals from the bank of efuse cells and signals that are output from the first and second sense amplifiers, and stores data representative of values of the signals in the storage circuit. The efuse security reads the data from the storage circuit and generates an alert signal having a state that indicates a security violation in response to data representative of the value of the signal from the first sense amplifier indicating a logic-0 value or data representative of the value of the signal from the second sense amplifier indicating a logic-1 value.

Efuse bank and associated anchor bits

The disclosure describes approaches for protecting a circuit design for a programmable integrated circuit (IC). A black key is generated from an input red key by a registration circuit implemented on the programmable IC, and the black key is stored in a memory circuit external to the programmable IC. The programmable IC is configured to implement a pre-configuration circuit, which inputs the black key from the memory circuit and generates the red key from the black key. A ciphertext circuit design is decrypted into a plaintext circuit design by the programmable IC using the red key, and the red key is erased from the programmable IC. The programmable IC is reconfigured with the plaintext circuit design.

Secure external key storage for programmable ICS

A programmable integrated circuit, includes an external port, a configuration memory, a hardened write path between the external port and the configuration memory and a soft read path between the configuration memory and the external port, wherein configuration data stored in the configuration memory is only read through the soft read path.

Secure configuration readback for programmable logic devices

A system generally relating to an SoC, which may be a field programmable SoC ('FPSoC'), is disclosed. In this SoC, dedicated hardware includes a processing unit, a first internal memory, a second internal memory, an authentication engine, and a decryption engine. A storage device is coupled to the SoC. The storage device has access to a boot image. The first internal memory has boot code stored therein. The boot code is for a secure boot of the SoC. The boot code is configured to cause the processing unit to control the secure boot.

Secured booting of a field programmable system-on-chip including authentication of a first stage boot loader to mitigate against differential power analysis

Approaches for configuring a programmable integrated circuit (IC) are disclosed. Encrypted configuration data is input to the programmable IC, and the encrypted configuration data is stored in configuration memory of the programmable IC. As the encrypted configuration data is input, a determination is made as to whether or not the encrypted configuration data is authentic. In response to the encrypted configuration data being authentic, the encrypted configuration data is read from the configuration memory and decrypted, and the decrypted configuration data is stored back in the configuration memory.

Programmable integrated circuit with DPA-resistant decryption

Approaches for restricting the use of an integrated circuit (IC) are described. In response to receiving an encrypted configuration bitstream, a cryptographic key is retrieved from an internal memory of the IC and the encrypted configuration bitstream is decrypted using the cryptographic key to produce a decrypted configuration bitstream. A first signature value of the decrypted configuration bitstream is calculated. A second signature value is retrieved from a write-once memory of the IC. In response to the first signature value being different from the second signature value, configuration of the IC with the bitstream is prevented. In response to the first signature value being equal to the second signature value, configuration of the IC with the bitstream is permitted.

Method and apparatus for restricting the use of integrated circuits

A circuit for enabling communication of cryptographic data in an integrated circuit is disclosed. The circuit comprises a first interface coupled to receive data having a first security level; a second interface coupled to receive data having a second security level; a cryptographic application; and a routing block coupled between the first and second interfaces and the cryptographic application, the routing block comprising configurable logic, wherein the routing block is configurable to selectively route the data having the first security level by way of the first interface and to route data having the second security level by way of the second interface. A method of enabling communication of cryptographic data in an integrated circuit is also disclosed.

Circuit for and method of enabling communication of cryptographic data

According to an embodiment, a method of preventing the alteration of a stored data value is disclosed. The method comprises coupling a first electronic fuse to an output control circuit; coupling a second electronic fuse to the output control circuit; decoding the states of the first electronic fuse and the second electronic fuse after a first processing step to generate a first decoded state; and decoding the states of the first electronic fuse and the second electronic fuse after a second processing step to generate a second decoded state different from the first decoded state; wherein the output control circuit maintains the second decoded state after an attempt to alter a state of an electronic fuse of the first electronic fuse and the second electronic fuse. A circuit for preventing the alteration of a stored data value is also described.

Method of and circuit for preventing the alteration of a stored data value

In one embodiment, a cryptographic device is provided. The cryptographic device includes a persistent memory and a decryption control circuit coupled to the persistent memory. The decryption control circuit is configured to receive an encrypted data stream and decrypt a first portion of the encrypted data stream using a first cryptographic key stored in the persistent memory, the first portion including a second cryptographic key. The decryption circuit is configured to decrypt a second portion of the encrypted data stream using the second cryptographic key, the second portion of the encrypted data stream including payload data.

Growing community of inventors

Rio Rancho, NM, United States of America

Edward S Peterson