Xilinx, Inc.

Edward S McGettigan

Nicolas J Camilleri

Bradley K Fross

Stephen M Trimberger

David P Schultz

F Erich Goetting

James M Simkins

Neil G Jacobson

Raymond Kong

Matthew H Klein

Brian Philofsky

Anthony J Collins

Jeffrey V Lindholm

Subodh Gupta

Michael E Peattie

Kenneth J Stickney, Jr

Jennifer T Tran

Kevin L Bixler

Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.

System and methods for reducing clock power in integrated circuits

A method of partially reconfiguring a field programmable gate array (FPGA) with at least one design that has interdesign routing with at least one other design programmed into the FPGA. A first configuration data set implements a first design in a first area of the FPGA, a second design in a second, non-overlapping area, and at least one bus macro that defines a bus interface between the first design and the second design. The bus interface includes a set of signal lines coupled to the first and second designs and logic that controls input and output of signals over the signal lines. A second configuration data set implements a modified version of the first design in the first area and does not implement any version of the second design. The FPGA is configured with the first configuration data set, and then partially configured with the second configuration data set.

Partial configuration of a programmable gate array using a bus macro and coupling the third design

Method and apparatus are described for providing analog capability with boundary-scanning for an integrated circuit. The integrated circuit includes a boundary-scan controller () coupled to an analog-to-digital converter (). An analog channel is selected for input to the analog-to-digital converter (). Analog information is converted to digital information by the analog-to-digital converter (), and then such digital information may be stored in data registers () for reading out via the boundary-scan controller ().

Boundary-scan circuit used for analog and digital testing of an integrated circuit

Systems and methods utilizing virtual input/output (VIO) modules in PLDS. One or more VIO modules are embedded in a PLD along with the user circuit to be controlled and monitored. The VIO module includes a control module that acts as a virtual input module for the user circuit, and can optionally include a status module that acts as a virtual output module for the user circuit. A bi-directional data interface is provided between the user circuit and the VIO modules, and between the VIO modules and a communication module. The communication module is coupled through input/output pads of the PLD to an external communication link, and hence to a host computer in which resides software that controls the communication link. Thus, by interfacing with the host computer, a user can control the user circuit via the control modules and monitor output signals from the user circuit via the status modules.

Systems and methods of utilizing virtual input and output modules in a programmable logic device

A bus macro for use as a routing resource for partial reconfiguration of a field programmable gate array (FPGA) with a design that has interdesign routing with at least one other design programmed into the FPGA comprises: at least one row of bus lines disposed within the FPGA between at least two design areas; a first set of gates disposed within the FPGA for controlling a routing of signals over the at least one row of bus lines from a first design area to a second design area of the FPGA according to a first routing configuration embedded in the first design area; and a second set of gates disposed within the FPGA for controlling a routing of signals over the at least one row of bus lines from the second design area to the first design area of the FPGA according to a second routing configuration embedded in the second design area. A method of partially reconfiguring a field programmable gate array (FPGA) with at least one design that has interdesign routing with at least one other design programmed into the FPGA is also disclosed utilizing at least one bus macro.

Partial reconfiguration of a programmable gate array using a bus macro

A clock template includes digital programming information for programming clock frames of a programmable gate array (PGA). The digital programming information represents a number of different clock configurations that correspond to various designs in the PGA. In one embodiment, the digital programming information includes a bit stream for partially reconfiguring the PGA. In another embodiment, the digital programming information is embedded in digital programming information of at least one of the designs. Methods of configuring a PGA with different designs having different clocking configurations by utilizing the clock template are also disclosed.

Clock template for configuring a programmable gate array

A method of configuring an FPGA lookup table to implement both exact and relative matching comparators is disclosed. Examples of exact matching of two variables, exact matching of a variable to a constant, relative matching (greater than) of a variable to a constant, and combined exact and relative matching are discussed. Use of the comparator to trigger a logic analyzer to collect data is discussed.

Logic block used as dynamically configurable logic function

In an FPGA having four-input lookup tables (LUTs) with parallel two-input AND gates receiving two of the four LUT input signals, associated registers, and a carry chain receiving one input signal from the AND gate output, a loadable up-down counter is formed by connecting the register output to one of the terminals serving as both a LUT input terminal and an AND gate input terminal. A load control signal is connected to another input terminal common to the LUT and the AND gate. Thus the AND gate disables the carry chain during loading of the counter and applies the count value to the carry chain during counting.

Loadable up-down counter with asynchronous reset

A method of computer aided design of coarse grain FPGA's by employing a library of selected primitive cells, defining the connection classes useful in the FPGA design, and assigning appropriate connection classes to the inputs and outputs of the respective primitive cells. The primitive cells and defined interconnections used therein have accurately established timing and power parameters thereby enabling more accurate assessments of static timing and power consumption for the entire FPGA design. Moreover, the method of the present invention results in placement directives which then serve as connection criteria in carrying out subsequent place and route algorithms. One such placement directive is implemented as a 'local output' (LO) of some of the primitive cells which implies that that particular output must be connected to another primitive cell input within the local configurable logic block (CLB). Another such placement directive is obtained by using a plurality of virtual buffers. They're referred to as virtual buffers because they serve only a design function and do not actually exist in a CLB. The virtual buffers provide placement directives such as to connect a primitive cell output to another CLB input within some prescribed geographical limit such as within 4 or 6 CLBs of the one in which the buffer is 'located'.

Growing community of inventors

San Jose, CA, United States of America

Edward S McGettigan