Atmel Corporation

Edward S Hui

George J Korsh

Dirk R Franklin

Anil Gupta

Steven J Schumann

Nicola Telecco

Jason Guo

Vijay P Adusumilli

Kris Li

Mehdi Jazayeri

A sense amplifier circuit comprises first and second cross-coupled inverters to produce a latch with first and second power supply nodes. The first latch power supply node couples a first power supply potential to the latch when the sense amplifier is operating in a read-out mode. The second latch power supply node couples a second power supply potential to the latch when the sense amplifier operates in the read-out mode. The first and second latch power supply nodes are further configured to couple an equalization potential to the first and second power supply nodes when the latch is operating in an equalization mode.

Sense amplifier for flash memory device

A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The memory circuit is fabricated on a second integrated circuit chip and includes a column decoder, a row decoder, a control register, and a data register. A memory-controller interface area includes a first plurality of die bond pads on the first integrated circuit chip and a second plurality of die bond pads on the second integrated circuit chip such that the first and second integrated circuit chips may be die-bonded together. A single controller circuit may interface with a plurality of memory circuits, thus further reducing overall costs as each memory circuit does not require a dedicated controller circuit.

Nonvolatile semiconductor memory apparatus

A continuity test mode circuit in an integrated circuit device having a means for switching between a continuity test mode and a normal operating mode. The test mode is characterized by one or more input pins being in direct electrical connection with one or more output pins to enable the pins and the chip packaging and chip socket and circuit board to be tested for continuity. In normal operating mode, the operation of the chip is not affected by the test mode circuitry. The continuity test mode circuit allows for testing of device-socket and/or device-board continuity in order to ensure accurate testing and programming of the device.

Input/output continuity test mode circuit

A non-volatile memory device having a main memory that operates synchronously with the system clock and an asynchronous boot block. The boot block can be activated to operate asynchronously upon initial power up or can be switched from synchronous to asynchronous mode upon receipt of a command signal by control logic circuitry within the device.

Independent asynchronous boot block for synchronous non-volatile memory devices

A low voltage EPROM which increases its reading speed by charging a word line to a voltage higher than vcc during a read operation. Two voltage pumps, which alternately place charge on a word line, receive control signals of opposite phase from a temperature insensitive oscillator. The voltage from the two voltage pumps passes through a zero threshold voltage n-type pass device to a word line. The zero threshold voltage n-type pass device receives its control signal from a third voltage pump. In order to make the low voltage EPROM compatible with standard 5V programmers, each output driving circuit consists of a large output driver used under low voltage V.sub.cc conditions and a smaller output driver used under standard 5V V.sub.cc conditions.

High speed, low voltage non-volatile memory

A transistor construction having a gate electrode meandering in a serpentine manner between interlacked comb-like drain and sources electrodes. The construction is equivalent to parallel transistors with series-connected gates, and the resistivity of the gate electrode forms a RC delay line in which transistors furthest from the gate drivers lag behind those which are closest. Accordingly, the transistor construction turns on or off gradually. The construction is useful as part of a CMOS output driver to memory chips and the like where the inductance of bondwires and the package leads normally cause noise spikes. The transistor construction reduces the current slew rate during switching so that less noise occurs on the chip supply lines. Another embodiment is made up of up to four parallel connected blocks of series-connected-gates. Multiple gate turn-off drivers are provided in a modified output driver, connected in parallel to each series-connected gate block, to insure that the transistor block turns off more rapidly than it turns on.

Growing community of inventors

Cupertino, CA, United States of America

Edward S Hui