International Business Machines Corporation

Edward Robert Vanderslice

Thomas Basilio Genduso

Richard Allen Kelley

Donald Ingerman

Robert Andrew Lackman

Data is transferred over a bus from one device to another, or between one device and another system resource, such as a central processor. This data is classified into one of several types. 'Hard real time' data must be transferred within a specified time limit or 'deadline' and it is unacceptable to miss a deadline. 'Soft real time' data should be transferred before a deadline and, although some missed deadlines are tolerable, the lower the number of missed deadline the better. 'Loss sensitive' data has no deadlines, but any loss of data is unacceptable. 'Non-real time' data also has no deadlines, but the lower the time delay in transferring the data the better. The intelligence that controls the transfer of data and schedules access to the bus is distributed throughout the system. Part of this scheduling intelligence is included in the bus arbiter, while the remainder is incorporated in the devices themselves.

Distributed scheduling for the transfer of real time, loss sensitive and

A computer system is provided which includes a central processing unit (CPU), a main memory, cache memory and a cache controller. The CPU generates a first CPU control signal indicating whether a CPU request is a request for instruction or data and a second CPU control signal indicating whether a request is for retrieving information from memory or for storing information into the memory. The cache controller includes prefetch logic which is responsive to the type of request from the CPU, such as, for example, instruction or data, read or write, for determining the amount of data to be prefetched into the cache memory from the main memory.

Computer system having cache prefetching amount based on CPU request

An improved memory controller within a data processing system having a look-aside cache architecture is disclosed. The data processing system includes a processor having an upper level cache associated therewith, a memory controller having an associated controller memory, a processor bus coupled between the processor and the memory controller, and a main memory. The data processing system further includes a lower level cache coupled to the processor bus in parallel with the processor and memory controller. According to a first aspect of the present invention, the memory controller includes logic, which in response to receipt of a write request that will not be serviced by the lower level cache and for which the associated data is not a replaced modified cache line, stores the associated data within the controller memory associated with the memory controller, thereby optimizing data storage within the data processing system. According to a second aspect of the present invention, the memory controller includes logic, which in response to receipt of a request for information residing only in main memory, fetches the requested information from main memory and stores additional information adjacent to said requested data in main memory within a prefetch buffer, thereby minimizing access time to the prefetched information.

Data processing system memory controller that selectively caches data

A Central Processing Unit is provided having an instruction processor for determining CPU instruction types. An instruction detector is included in the CPU for detecting whether a determined instruction is a non-cacheable repeat operation instruction. The CPU has an execution unit for executing instruction and for outputting a CPU signal indicating whether data associated with an instruction is cacheable.

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Boca Raton, FL, United States of America

Edward Robert Vanderslice