Wolfspeed, Inc.

Cree Gmbh

Cree.inc.

Other

Edward Robert Van Brunt

Daniel Jenner Lichtenwalner

Vipindas Pala

Lin Cheng

Brett Hull

Alexander V Suvorov

Sei-Hyung Ryu

Anant Kumar Agarwal

Thomas E Harrington, Iii

Shadi Sabri

John Williams Palmour

Robert Tyler Leonard

Matthew David Conrad

Philipp Steinmann

Qingchun Zhang

James Theodore Richmond

Kijeong Han

Brice McPherson

Scott Thomas Allen

Joe W McPherson

Jae-Hyung Park

Jae Hyung Park

Vaishno Dasika

Adam Barkley

Zachary Cole

Edward Lloyd Hutchins

Craig Capell

Matt N McCain

Joohyung Kim

Kraig J Olejniczak

In-Hwan Ji

A method of analyzing semiconductor wafers includes capturing a first image of a first crystalline material, etching a first surface of the first crystalline material to delineate etch defects in the first crystalline material, and capturing a second image of first crystalline material after etching the first surface of the first crystalline material. Based on the second image, labels of etch defects delineated in the first surface of the first crystalline material are generated. The first image and the labels of etch defects are spatially coordinated to form a defect map identifying one or more defects in the first image based on the delineated etch defects, and based on the defect map and nondestructive data obtained from a second crystalline material, defects in the second crystalline material are identified.

Nondestructive characterization for crystalline wafers

A transistor semiconductor die includes a first current terminal, a second current terminal, and a control terminal. A semiconductor structure is between the first current terminal, the second current terminal, and the control terminal and configured such that a resistance between the first current terminal and the second current terminal is based on a control signal provided at the control terminal. Short circuit protection circuitry is coupled between the control terminal and the second current terminal. In a normal mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is greater than a voltage of the control signal. In a short circuit protection mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is less than a voltage of the control signal.

Device design for short-circuit protection of transistors

Semiconductor devices, and more particularly semiconductor devices with improved edge termination structures are disclosed. A semiconductor device includes a drift region that forms part of an active region. An edge termination region is arranged along a perimeter of the active region and also includes a portion of the drift region. The edge termination region includes one or more sub-regions of an opposite doping type than the drift region and one or more electrodes may be capacitively coupled to the drift region by way of the one or more sub-regions. During a forward blocking mode for the semiconductor device, the one or more electrodes may provide a path that draws ions away from passivation layers that are on the edge termination region and away from the active region. In this manner, the semiconductor device may exhibit reduced leakage, particularly at higher operating voltages and higher associated operating temperatures.

Edge termination structures for semiconductor devices

An example method includes obtaining a workpiece image of a semiconductor workpiece. The example method includes providing the workpiece image as input to a machine-learned encoding model. The example method includes obtaining an output from the machine-learned encoding model, the output includes an encoding corresponding to the semiconductor workpiece. The example method includes determining one or more characteristics of the semiconductor workpiece based at least in part on the encoding or modifying a semiconductor manufacturing process based at least in part on the encoding.

Multi-scale autoencoders for semiconductor workpiece understanding

Semiconductor devices, and in particular protection structures for semiconductor devices that include sensor arrangements are disclosed. A semiconductor device may include a sensor region, for example a current sensor region that occupies a portion of an overall active area of the device. The current sensor region may be configured to provide monitoring of device load currents during operation. Semiconductor devices according to the present disclosure include one or more protection structures that are configured to allow the semiconductor devices to withstand transient voltage events without device failure. A protection structure may include an insulating layer that is provided in a transition region between a device region and the sensor region of the semiconductor device. In the example of an insulated gate semiconductor device, the insulating layer of the protection structure may include a material with a greater breakdown voltage than a breakdown voltage of a gate insulating layer.

Protection structures for semiconductor devices with sensor arrangements

Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.

Power semiconductor device with reduced strain

A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers.

Vertical semiconductor device with improved ruggedness

Shielding techniques are used to provide an embedded sensor element such as a temperature sensing element on a wide bandgap power semiconductor device. A semiconductor device may include a drift layer and an embedded sensor element. The drift layer may be a wide bandgap semiconductor material. A shielding structure is provided in the drift layer below the embedded sensor element. The embedded sensor element may be provided between contacts that are in electrical contact with the shielding well. The distance between the contacts may be minimized. A noise reduction well may be provided between the contacts to further isolate the embedded sensor element from parasitic signals.

Wide bandgap semiconductor device with sensor element

A transistor semiconductor die includes a drift layer, a first dielectric layer, a first metallization layer, a second dielectric layer, a second metallization layer, a first plurality of electrodes, and a second plurality of electrodes. The first dielectric layer is over the drift layer. The first metallization layer is over the first dielectric layer such that at least a portion of the first metallization layer provides a first contact pad. The second dielectric layer is over the first metallization layer. The second metallization layer is over the second dielectric layer such that at least a portion of the second metallization layer provides a second contact pad and the second metallization layer at least partially overlaps the first metallization layer. The transistor semiconductor die is configured to selectively conduct current between the first contact pad and a third contact pad based on signals provided at the second contact pad.

Transistor semiconductor die with increased active area

Nondestructive characterization of crystalline wafers is provided, including defect detection, identification, and counting. Certain aspects relate to development of nondestructive, high fidelity defect characterization and/or dislocation counting methods based on deep neural networks. Certain aspects relate to nondestructive methods for defect characterization of silicon carbide (SiC) wafers. By subjecting SiC wafers to nondestructive defect characterization, SiC wafers in their final state may be characterized and subsequently used for device fabrication, vastly reducing the expense of the characterization process. Nondestructive defect characterization also allows for increased sampling and improved feedback loops between crystalline growth process development and subsequent device production.

Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material. A shielding pattern is provided in an upper portion of the drift region in an active region of the device and a termination structure is provided in the upper portion of the drift region in a termination region of the device. A gate trench extends into an upper surface of the semiconductor layer structure. The semiconductor layer structure includes a semiconductor layer that extends above and at least partially covers the termination structure.

Power semiconductor devices having gate trenches and buried edge terminations and related methods

Power semiconductor devices comprise a gate pad, a plurality of gate fingers, and a first gate resistor and a first switch that are coupled between the gate pad and the gate fingers.

Semiconductor devices having asymmetric integrated gate resistors for balanced turn-on/turn-off behavior

Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10&#xb0; and 30&#xb0; from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/&#x2212;1.5&#xb0; of a crystallographic axis of the silicon carbide material forming the drift region.

Superjunction power semiconductor devices formed via ion implantation channeling techniques and related methods

A semiconductor device includes a semiconductor layer structure comprising a source/drain region, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer. The source/drain region comprises a first portion comprising a first dopant concentration and a second portion comprising a second dopant concentration. The second portion is closer to a center of the gate electrode than the first portion.

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Raleigh, NC, United States of America

Edward Robert Van Brunt