Bull Hn Information Systems, Inc.

Edward R Salas

Jeffrey S Somers

Raymond D Bowden, Iii

Marc E Sanfacon

In accordance with the present invention, there is provided a system for logging an error that occurred in a multi-chip memory storage device in a data processing system. The system has a mechanism for detecting an error and for receiving data and check bits associated therewith. The mechanism for detecting an error generates syndrome bits as a function of the data and of the check bits. Connected to the error detecting mechanism is an error logging mechanism which is adapted to receive the syndrome bits and to determine the chip in which the error occurred.

Memory controller with error logging

A system and method for detecting an error that occurred in a multi-chip memory storage device in a data processing system. The system detects an error and receives data and check bits associated therewith. A process that uses the principle of scrubbing and incorporates high speed error flags distinguishes between hard and soft errors.

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Lowell, MA, United States of America

Edward R Salas