Freescale Semiconductor,inc.

Other

Motorola Corporation

Edward R Prack

Marc Alan Mangrum

George R Leal

Robert Joseph Wenzel

Jie-Hua Zhao

David G Wontor

Brian D Sawyer

Young Sir Chung

James Jen-Ho Wang

Vijay Sarihan

Lei L Mercado

Treliant Fang

Frank W Fischer

A circuit device is placed within an opening of a conductive layer which is then partially encapsulated with an encapsulant so that the active surface of the circuit device is coplanar with the conductive layer. At least a portion of the conductive layer may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device may be placed on a conductive layer such that an active surface of circuit device is between conductive layer and an opposite surface of circuit device. The conductive layer has at least one opening to expose the active surface of circuit device. The encapsulant may be electrically conductive or electrically non-conductive.

Circuit device with at least partial packaging and method for forming

A circuit device () is placed within an opening of a conductive layer () which is then partially encapsulated with an encapsulant () so that the active surface of the circuit device () is coplanar with the conductive layer (). At least a portion of the conductive layer () may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device () may be placed on a conductive layer () such that an active surface of circuit device () is between conductive layer () and an opposite surface of circuit device (). The conductive layer () has at least one opening () to expose the active surface of circuit device (). The encapsulant () may be electrically conductive or electrically non-conductive.

Circuit device with at least partial packaging, exposed active surface and a voltage reference plane

In accordance with one embodiment, a stress buffer () is formed between a power metal structure () and passivation layer (). The stress buffer () reduces the effects of stress imparted upon the passivation layer () by the power metal structure (). In accordance with an alternative embodiment, a power metal structure (A) is partitioned into segments (), whereby electrical continuity is maintained between the segments () by remaining portions of a seed layer () and adhesion/barrier layer (). The individual segments () impart a lower peak stress than a comparably sized continuous power metal structure ().

Semiconductor power device with shear stress compensation

In one embodiment, circuit device () is placed within an opening of a conductive layer () which is then partially encapsulated with an encapsulant () so that the active surface of the circuit device () is coplanar with the conductive layer (). In this embodiment, at least a portion of the conductive layer () may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device () is placed on a conductive layer () such that an active surface of circuit device () is between conductive layer () and an opposite surface of circuit device (). In this embodiment, conductive layer () has at least one opening () to expose the active surface of circuit device (). The encapsulant () may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.

A method of manufacturing a semiconductor component having a layer ( ) comprised of polyimide includes using an etchant that is at least partially composed of aminopropanediol to etch the layer comprised of polyimide. The etchant can also include a solvent, a diluent, and water.

Method of manufacturing a semiconductor component and polyimide etchant therefor

In accordance with one embodiment, a stress buffer ( ) is formed between a power metal structure ( ) and passivation layer ( ). The stress buffer ( ) reduces the effects of stress imparted upon the passivation layer ( ) by the power metal structure ( ). In accordance with an alternative embodiment, a power metal structure ( A) is partitioned into segments ( ), whereby electrical continuity is maintained between the segments ( ) by remaining portions of a seed layer ( ) and adhesion/barrier layer ( ). The individual segments ( ) impart a lower peak stress than a comparably sized continuous power metal structure ( ).

Growing community of inventors

Austin, TX, United States of America

Edward R Prack