Intel Corporation

Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Edward R Helder

Ashish Gupta

Fangxing Wei

Francis X Schumacher

Denny M Renfrow

Chengting Zhao

Some embodiments provide a synchronization circuit to receive a synchronization signal, the synchronization signal substantially synchronized with a data transition, to synchronize the synchronization signal with a clock signal, and to generate a load signal based on the synchronized synchronization signal. Also provided may be a ring counter to receive the load signal from the synchronization circuit and to circularly propagate the load signal.

Synchronized serial interface

A system and method for maintaining lock of a phase locked loop within an integrated circuit during both a normal operation mode and a test mode, and during switching from the normal operation mode to the test mode, is disclosed. The method includes closing a phase locked loop feedback path of the phase locked loop with a real clock signal from a real clock tree during the normal operation mode. The real clock tree is selectively halted, thereby transitioning from the normal operation mode to the test mode. The phase locked loop feedback path of the phase locked loop is closed with a copy of a clock signal from a copy clock tree such that the phase locked loop maintains lock. The steps of halting the real clock and closing the phase locked loop feedback path with a copy clock signal are completed during a single clock cycle such that lock is maintained during switching from the normal operation to the test mode.

System and method for maintaining lock of a phase locked loop feedback during clock halt

An edge generation circuit phase delays pulses of a first signal propagated on an integrated circuit. The edge generation circuit includes a first variable delay circuit located on the integrated circuit, a delay line located off the integrated circuit and a second variable delay circuit located on the integrated circuit. The first variable delay circuit receives the first signal and produces a second signal which is in phase with the first signal. The delay line receives the second signal and produces a third signal. The third signal is delayed in phase from the second by a precise amount. The second variable delay circuit receives the third signal from the delay line and produces a fourth signal. The fourth signal is in phase with the third signal.

Logic edge timing generation

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Fremont, CA, United States of America

Edward R Helder