Koninklijke Philips Corporation N.V.

Vlsi Technology, Inc.

Edward Michael Petryk

Peter Chambers

Lonnie Calvin Goff

Subramanian S Meiyappan

Scott E Harrow

Brian Logsdon

Varaprasad Vajjhala

George Parker Crouse

The present invention facilitates automation of system on a chip (SoC) design, manufacture and verification in a convenient and efficient manner. In one embodiment, a SoC netlist builder and verification computer system of the present invention includes a user interface module, a parameter application module, an expert system module and a chip level netlist generation module. The user interface module provides user friendly and convenient interfaces that facilitate easy entry and modification of user selections and parameters. The parameter application module interprets information supplied by the user module and the expert system module and creates directions (e.g., command lines) passed to other modules for execution. The expert system module analyzes information and automatically provides SoC building and verification data including automated addition of default architectural features, automated insertion of default parameters, and automated input of information to the verification module. The chip level netlist generation module automatically generates a chip level netlist, including the instantiation of internal IC devices and connections between the circuit blocks for internal signals. The verification module automatically generates a test bench and a logical verification environment including simulation models (e.g., a chip model and a system level model).

Computer system and method to dynamically generate system on a chip description files and verification information

Among the embodiments of the present invention is test equipment ( ) to test an integrated circuit ( ). The integrated circuit ( ) includes one or more processors and one or more communication devices ( ). The test equipment ( ) includes a responder integrated circuit ( ) that has at least one processor, several communication devices ( ), and one or more configuration connections ( ). The responder integrated circuit responds to commands from the first integrated circuit ( ) and a configuration established with the one or more configuration connections ( ) to test operation of the one or more communication devices ( ).

Multi-environment testing with a responder

The present invention comprises a multiple functional block integrated circuit device for connecting to an external peripheral component interconnect (PCI) bus. The present invention includes an integrated circuit adapted to be coupled to an external PCI bus. The integrated circuit includes a plurality of functional blocks. Each of the plurality of functional blocks performs a function and comprises either a master functional block or a target functional block. A target bus adapted to transmit data signals is integral with the integrated circuit. The target bus is coupled to each of the plurality of functional blocks. A master bus adapted to transmit data signals is also integral with the integrated circuit. The master bus is coupled to each master functional block. A target bus interface integral with the integrated circuit is coupled to the target bus. The target bus interface is adapted to be coupled to the external PCI bus and to each of the plurality of functional blocks and interfaces each of the plurality of functional blocks to the external PCI bus. A master bus interface integral with the integrated circuit is coupled to the master bus. The master bus interface is adapted to be coupled to the external PCI bus and to each master functional block and interfaces each master functional block to the external PCI Bus.

Method and system for an extensible on silicon bus supporting multiple

A multiple peripheral component interconnect (PCI) agent integrated circuit device for connecting to an external PCI bus. In one embodiment, the present multiple PCI agent integrated circuit device includes, an integrated circuit which is adapted to be coupled to an external PCI bus. The integrated circuit includes an internal PCI bus built in. The internal PCI bus is adapted to transmit data signals thereon, and is further adapted to couple to the external PCI bus via a connector. A plurality of PCI agents are built into the integrated circuit, wherein each of the plurality of PCI agents are capable of performing an independent function. Each of the plurality of PCI agents are coupled to the internal PCI bus. A predictive arbiter is built into the integrated circuit and is coupled to both the internal PCI bus and to the plurality of PCI agents. The predictive arbiter arbitrates between the PCI agents for ownership of the internal PCI bus.

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Pheonix, AZ, United States of America

Edward Michael Petryk