Apple Inc.

Arm Limited

Edward Martin McCombs, Jr

Michael R Seningen

Greg M Hess

Rahul Mathur

Hsin-Yu Chen

Ben D Jarrett

Daniel C Chow

Alexander E Runas

Andrew David Tune

Sean James Salisbury

Kenneth W Jones

Phani Raja Bhushan Chalasani

Yew Keong Chong

Andy Wangkun Chen

Stephen C Horne

Akshay Kumar

Rajiv Kumar Sisodia

William V Miller

Michael A Dreesen

Munish Kumar

Ayush Kulshrestha

Kumaraswamy Ramanathan

Jason A Frerich

Chetan C Kamdar

Derrick Andrew Leach

Kyung Woo Kim

Christopher M Goertz

Thomas J Best

Gaurav Kumar

A method for write operations to memory include starting write operations for writing n words in a same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; loading one or more additional words of the n words, each during a corresponding one or more additional clock cycles; triggering the n words to be stored in the memory; and closing the write operations for the writing of the n words during a final clock cycle, whereby the n words are written in n+1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle. The write circuitry performing the aforementioned operations can also perform write operations for a single word in two clock cycles.

Increased throughput for writes to memory

Various implementations described herein are directed to a device having memory circuitry with bitlines coupled to an array of bitcells. The device may include precharge circuitry that precharges the bitlines during modes of operation including a standby mode of operation and an active mode of operation. In some instances, the precharge circuitry may include a low power mode of operation that prevents precharge of the bitlines during the standby mode of operation.

Precharge circuitry for use with bitlines

An on-chip memory is provided. The memory includes wordline sections, input/output (I/O) circuitry, and control circuitry. Each wordline section includes a number of wordlines, and each wordline section is coupled to a different wordline control circuitry. The control circuitry is configured to, in response to receiving an access request including an address, decode the address including determine, based on the address, an associated wordline, and determine, based on the associated wordline, an associated wordline section. The control circuitry is further configured to apply power to wordline control circuitry coupled to the associated wordline section, and access the address.

Dynamic way-based variable pipeline architecture for on-chip memory

Dynamic power management for an on-chip memory, such as a system cache memory as well as other memories, is provided. The memory includes wordline sections, input/output (I/O) circuitry, and control circuitry. Each wordline section includes a number of wordlines, and each wordline section is coupled to a different wordline control circuitry. The control circuitry is configured to, in response to receiving an access request including an address, decode the address including determine, based on the address, an associated wordline, and determine, based on the associated wordline, an associated wordline section. The control circuitry is further configured to apply power to wordline control circuitry coupled to the associated wordline section.

Dynamic power management for on-chip memory

Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.

Circuitry and method

A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.

Burst read with flexible burst length for on-chip memory

A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

System control using sparse data

Various implementations described herein are directed to a device having memory with banks of bitcells with each bank having a bitcell array. The device may have header circuitry that powers-up a selected bank and powers-down unselected banks during a wake-up mode of operation. In some instances, only the selected bank of the memory is powered-up with the header circuitry during the wake-up mode of operation.

Power-up header circuitry for multi-bank memory

Various implementations described herein are directed to a method. The method may receive an address to access data stored in memory. The method may enable a data access pipeline to perform memory access operations so as to access the data stored in the memory based on the address. The method may dynamically adjust the data access pipeline during the memory access operations so as to output the data based on the address.

Dynamically adjustable pipeline for memory access

One implementation described herein is related to a device having memory with sense amplifiers and precharge blocks arranged in an array with a first side and a second side. The first side has first sense amplifiers and first precharge blocks coupled together with first bitlines, and the second side has second sense amplifiers and second precharge blocks coupled together with second bitlines. The device has a first delay block coupled to the first precharge blocks in the first side of the array, and the first delay block delays precharge of the first bitlines with a first precharge burst in a multi-burst precharge event. The device has a second delay block coupled to the second precharge blocks in the second side of the array, and the second delay block delays precharge of the second bitlines with a second precharge burst in the multi-burst precharge event.

System cache peak power management

Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.

Wordline driver architecture

Techniques for implementing a storage array write driver with a reduced-power boost circuit. An apparatus may include a bit cell configured to store data, a bit line circuit coupled to convey data to the bit cell, a write driver circuit configured to transmit write data to the bit cell via the bit line circuit, and a boost circuit that is distinct from the write driver circuit. The boost circuit may be selectively coupled to drive the bit line circuit below a ground voltage dependent on activation of a boost signal and the write data being in a logic low state. The boost circuit may also be coupled to the bit line circuit at a location that is closer to the bit cell than to the write driver circuit, and may be sized to discharge the bit line circuit without being sized to discharge internal capacitance of the write driver.

Growing community of inventors

Austin, TX, United States of America

Edward Martin McCombs, Jr