Gan Systems Inc.

Infineon Technologies Canada Inc.

Edward MacRobbie

Nan Xing

Robert Wayne Mounger

Ahmad Mizan

Lucas Andrew Milner

Sridhar Ramaswamy

Yinglai Xia

Hossein Mousavian

Krishnaswamy Nagaraj

Zhemin Zhang

Yalong Li

Thomas William Macelwee

Ahmad Mizannojehdehi

A circuit that includes a power transistor and at least one sense transistor and that uses the control drive terminal to not only control the power transistor and the sense transistor, but also to provide power to a current sense circuit. The control nodes of the power transistor and sense transistor are connected, and the input nodes of the power transistor and the sense transistor are also connected. The current sense circuit is connected to the sense transistor control node and is configured to detect current passing through the sense transistor. The current sense circuit is also connected to the control drive terminal and is configured to draw power from the control drive terminal when a high control signal is present on the control drive terminal. Accordingly, the current sense circuit does not require an independent fixed high voltage supply in order to operate.

Circuit with power transistor and current sense that uses control drive as power source

A voltage supply circuit that generates a voltage on a voltage supply node. The voltage supply circuit includes an adjustable capacitor, an alternating voltage source, a charge source, and an adjusting circuit. When the alternating voltage on the second capacitor terminal transitions low, the voltage on the first capacitor terminal also becomes low, and the charge source provides charge to the first capacitor terminal of the adjustable capacitor. When the alternating voltage on the second capacitor terminal transitions high, the voltage on the first capacitor terminal also becomes high, and charge is thereby pumped from the first capacitor terminal to the voltage supply node. The adjusting circuit periodically samples the voltage on the voltage supply node, and adjusts the capacitance of the adjustable capacitor to increase or decrease that voltage.

Charge pumping using adjustable capacitor

A current sense circuit that allows for accurate sensing of a power current that flows through a power transistor as the power transistor ages. The circuit includes the power transistor, a sense transistor and a pull-up component. The control nodes of the power transistor and the sense transistor are connected, causing the power transistor and sense transistor to be on or off simultaneously. The pull-up component is connected between the input node of the power transistor and the input node of the sense transistor. When power is provided to the pull-up component, and when each of the power transistor and sense transistor are off, the pull-up component forces a voltage present at the sense transistor input node to be approximately equal to a voltage present at the power transistor input node, causing the sense and power transistors to age together.

Current sensing by using aging sense transistor

A power transistor circuit suppling an internal voltage to an internal voltage supply node. The power transistor circuit includes external terminals, to each of which signals and/or voltages are applied, for each of the input node, output node and control node of the power transistor. The power transistor circuit includes the power transistor, a current draw transistor, a first diode connected between an external control terminal and the internal voltage supply node, and a second diode connected between the current draw transistor output node and the internal voltage supply node. The power transistor circuit includes a charge pump that receives power from the internal voltage supply node and outputs a voltage to the control node of the current draw transistor. In operation, the internal voltage supply node receives power from the external control terminal via the first diode, or an external input terminal via the current draw transistor and the second diode.

Power transistor circuit that generates internal voltage supply

A GaN semiconductor power switching device (Q) comprising an integrated ESDprotection circuit is disclosed, which is compatible with driving Qwith a positive gate-to-source voltage Vgs for turn-on and a negative Vgs for turn-off, during normal operation. The ESD protection circuit is connected between a gate input of Qand a source of Q, and comprises a clamp transistor Q1, a positive trigger circuit and a negative trigger circuit, for turning on the gate of the clamp transistor Q1 responsive to an ESD event at the gate input of Q. The positive and negative trigger circuits each comprise a plurality of diode elements in series, having threshold voltages which are configured so that each of the positive trigger voltage and the negative trigger voltage can be adjusted. The ESD circuit topology requires smaller integrated resistors and can be implemented with reduced layout area compared to conventional integrated ESD circuits.

Integrated bidirectional ESD protection circuit for power semiconductor switching devices

Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a center of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

Device topology for lateral power transistors with low common source inductance

A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

Device topologies for high current lateral power semiconductor devices

Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a centre of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

Growing community of inventors

Nepean, Canada

Edward MacRobbie