Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Edward M Jacobs

Debendra Das Sharma

John Alan Wickeraad

Kent Andrew Dickey

Kenneth K Chan

Donald A Williamson

Thomas B Alexander

Julie W Moncton

Kathleen C Nix

An apparatus and method for an improved asynchronous communication channel between a transmitter and a receiver having separate clocks. The invention provides a simple implementation that solves both the overflow and the underflow problem using the same mechanism, and reduces complexity by elimination of the control split between the two clock domains. A first embodiment of the invention is a method for preventing packet underflow and packet overflow for packets sent across an asynchronous link between a transmitter and a receiver, including a buffer that can store a number of packets greater than an ideal number of packets. The method includes sending a predetermined number of drop-me warning packets and sending one or more drop-me packets from the transmitter to the receiver, receiving the predetermined number of drop-me warning packets and the one or more drop-me packets in the buffer, compensating for packet overflow when the number of packets is greater than the ideal number of packets in the buffer by skipping at least one drop-me packet, and compensating for packet underflow in the buffer when the number of packets is less than the ideal number of packets by stalling access to the buffer for one or more clock cycles. A second embodiment of the invention is an asynchronous link for packets sent between a transmitter having a first clock and a receiver having a second clock, including a buffer to receive the first clock from the transmitter and receive from the transmitter a number of packets equal to or different to a predetermined ideal number of packets, a write pointer, and a read pointer, and a read pointer control circuit to change the read pointer, wherein the buffer can receive drop-me packets, and the read pointer can skip a drop-me packet in the buffer.

Method and apparatus for preventing underflow and overflow across an asynchronous channel

A mechanism that includes an apparatus and method for ensuring that all transactions within any flow control class completes is herein provided. The mechanism includes a plunge transaction that is inserted in each pending transaction queue and which is transmitted to a particular destination device. All prior transactions in a flow control class are deemed to be complete when the destination device receives the plunge transactions in the flow control class.

Apparatus and method for completing transactions in all flow control classes

A processor-to-memory interface (PMI) for a multiprocessor computer system and a computer testing method are disclosed. The multi-processor computer system provides a processor-to-memory-bus interface for each microprocessor. Each processor-to-memory-bus interface translates between microprocessor and bus protocols and manages respective level-2 (L2) caches. In addition, each interface includes test-event hardware that, when enabled causes test events to be generated with a predetermined repetition rate. The test events are selected for having a non-zero probability of causing system events that are complex, rare and non-fatal. These include assertions of 'busy' and 'wait' conditions and corrections of single-bit cache errors. The test-event hardware includes a timing generator that determines when test events are to be generated, an event-flag register that determines which events are to be generated, and a test-event generator that generates test-events at the times determined by the timing generator. The timing generator can include a down counter and a register for holding a value to be entered into the counter upon initialization and reset. So that cache error-correction logic can be tested, a cache manager includes a cache-error generator that can generate cache errors at times determined by said timing generator. The test-event hardware permits system events of interest to be repeatedly generated during a test procedure without repeated intervention by a test program. The hardware test-event generation simplifies test program design and allows faster testing throughput.

Computer-system processor-to-memory-bus interface having

A multiprocessor computer architecture containing processor caches that are kept coherent, and in particular, a duplicate cache tag subsystem and method for maintaining duplicate cache tags, are disclosed. The tag width of duplicate cache tags for a processor cache is tailored to available integrated circuit surface area, or to device pin count, without significantly sacrificing system performance. Such partial duplicate tag width may also be reduced at any time during the integrated circuit design phase, should the available integrated circuit surface area or pin-availability decrease. The method disclosed involves requesting data from memory; reading a partial duplicate cache tag list to determine if there is a partial hit; taking the data from the memory if there is no match between a requested address and the partial duplicate cache tag list; holding the data in memory or a requestor module if there is a match between the requested address and the partial duplicate cache tag list; and interrupting processor operation to confirm that the partial duplicate cache tag corresponds to an actual cache tag. The data are taken from the cache if the partial duplicate cache tag matches the actual cache tag and cache status indicates that the data have been modified. The data are taken from memory if the partial duplicate cache tag does not match the actual cache tag or cache status indicates that the data have not been modified.

Method and apparatus for maintaining duplicate cache tags with

The present invention provides a protocol method for waiting the bus in a digital computer and an apparatus for implementing that protocol. By allowing the bus to continue running after a wait command has been asserted, modules on the computer bus are not required to respond instantly to the wait command. Information on the bus during the multiple cycles of the wait period is defined as invalid and valid data is driven on the bus after the wait period has expired. Bus driver modules are provided with a replay queue to replay, on the bus, data the driver module drove on the bus during the wait period if required.

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Mountain View, CA, United States of America

Edward M Jacobs