Intel Corporation

Edward M Babb

Christopher John Haid

Mase J Taub

Sanjay S Talreja

Robert E Larsen

Vishram P Dalvi

Bharat M Pathak

Prashanti Govindu

Marcus E Landgraf

Subramanyam Chandramouli

Ahmed T Sayed

Tahmid U Rahman

A block-alterable memory, e.g., a flash memory, having substantially zero erase time is coupled to host. The block-alterable memory includes a controller that reads block information from the memory on power up to determine if a block of the memory is usable. The controller updates block map latches only if the block is usable. The controller also updates block status latches according to the block information. Thus, information about each block of the memory is easily accessible in the latches when the block alterable memory becomes ready for use on power up.

Power-up implementation for block-alterable memory with zero-second erase time

In one embodiment, the present invention includes a method for performing a plurality of read operations on a nonvolatile array of a memory according to a single read command, and storing data from the plurality of read operations in a volatile array of the memory. In some embodiments, the nonvolatile array may be a flash-based array and the volatile array may be a random access memory.

Performing multiple read operations via a single read command

A method and apparatus to read information from a content addressable memory (CAM) cell of a nonvolatile memory is provided. The apparatus may be a nonvolatile memory that may include a first content addressable memory (CAM) cell, wherein the first CAM cell comprises a latch to store volatile binary information and to provide the volatile binary information to an output terminal of the first CAM cell.

Method and apparatus to read information from a content addressable memory (CAM) cell

A power supply lockout circuit that prevents corruption of nonvolatile writeable memory data is described. The power supply lockout circuit monitors the power supply signals from several power supplies. The power supply lockout circuit locks out commands writing to the nonvolatile writeable memory when any one of the monitored power supply signals coupled to the nonvolatile writeable memory is below a specified signal level. The power supply lockout circuit includes a detector which provides a lockout signal to the nonvolatile writeable memory when a power supply signal is less than a prespecified voltage. The power supply lockout circuit also includes a sampling circuit which provides other lockout signals to the nonvolatile writeable memory when a different power supply signal is less than a reference voltage.

Input/output power supply detection scheme for flash memory

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Rescue, CA, United States of America

Edward M Babb