Efficient Power Conversion Corporation

Alfred E. Mann Foundation for Scientific Research

Edward Lee

Ravi Ananth

Michael Chapman

Michael Andrew De Rooij

Robert A Beach

Jianjun Cao

John Stanley Glaser

Stephen L Colino

Zhikai Tang

Marco Palma

David C Tam

An integrated gate overvoltage protection circuit for protecting the gate of a main field effect transistor (FET). The gate protection circuit includes a blocking FET and a discharge FET connected between the gate and the drain of the main FET. The gate overvoltage protection circuit is configured to turn on both the first FET and the second FET in the event of a fault condition, such that charge from the gate of the main FET is discharged through the first FET and the second FET to the drain of the main FET, thereby protecting the gate of the main FET.

Integrated circuit for gate overvoltage protection of power devices

A circuit for synchronizing the turn-on/turn-off times of parallel FETs. The circuit includes a plurality of integrated circuits and a synchronizer. Each of the integrated circuits includes a power FET which operates in parallel with the power FETs of the other integrated circuits, and a phase detector. The phase detector receives and compares the phase output signal of the integrated circuit with the phase output signal of another integrated circuit, and provides signals to the synchronizer regarding the relative turn-on times of the power FETs based upon the phase output signals. The synchronizer, in response to the signals from each of the integrated circuits, reduces or increases the turn-on times of the power FETs, thereby synchronizing the turn-on times of the power FETs.

Synchronizing turn-on/turn-off times of parallel power FETs

A single-ended or differential level-shifting interface for GaN ICs that allows GaN ICs to be controlled with standard low-voltage CMOS level inputs. The logic level shift circuit is based on a resistive network is therefore insensitive to process and temperature variations, making it particularly well suited for implementation in a GaN IC. The resistive network for a single-ended input signal includes a first branch with a voltage divider connected to the input signal. The voltage divider of the first branch provides a level shifted and scaled input signal to the first input of a comparator at the optimal bias point of the comparator. The resistive network also includes a second voltage divider branch with hysteresis for providing a trip voltage to the second input to the comparator, also at the optimal bias point of the comparator. The comparator outputs complementary bipolar level shifted signals corresponding to the input signal.

Integrated GaN-based logic level translator

A gate driver circuit which integrates a synchronous bootstrap circuit in an isolation well of an integrated circuit, such that the synchronous bootstrap capacitor connected to the synchronous bootstrap circuit (and to the corresponding switch node of a power converter) can float with the corresponding switch node. Due to this feature, the voltage on one synchronous bootstrapping capacitor can be used to charge the synchronous bootstrapping capacitor of another (higher level) synchronous bootstrap circuit in a separate isolation well connected to a different switch node. As a result, the supply voltages for the synchronous bootstrap circuits in different isolation wells can all be supplied from a single ground referenced supply Vdd.

Universal power FET driver IC architecture

A bootstrapping gate driver circuit in which the size of the bootstrap capacitors is reduced. The gate-to-source voltage of the high side (pull-up) FET is pre-driven to an initial voltage (pre-driven voltage) before the bootstrap capacitor releases charge to charge up the gate-to-source voltage of the high side FET. This pre-driven voltage is applied through a pre-driven FET that allows current flow from the supply voltage to charge the gate of the high side FET to the pre-driven voltage. The pre-driven FET is turned on by a turn-on signal that occurs before the bootstrap capacitor releases charge. The pre-driven period (and hence, the pre-driven voltage) is determined from the time that the pre-driven FET begins to turn on, to the time that the bootstrap capacitor starts to release charge.

Pre-driven bootstrapping drivers

A bootstrapping circuit that utilizes multiple pre-charged capacitor voltages and applies the capacitor voltages to the high side FET of a GaN bootstrapping driver. During the pre-charging phase of the bootstrapping driver, multiple capacitors are charged in parallel to the supply voltage. During the driving phase of the bootstrapping driver, the capacitors are connected in series through a number of FETs and connected to the gate terminal of the high side FET of the bootstrapping driver. As a result, the gate-to-source voltage of the high side FET is equal to or greater than the supply voltage during the driving phase, increasing the driving capability of the high side FET and reducing the total required capacitance and die area of the bootstrapping driver.

Multi-voltage bootstrapping drivers

A circuit to enhance the driving capability of conventional inverting bootstrapping GaN drivers. When the inverting driver input is logic high and the driver output is off, the voltage stored on the first bootstrap capacitor for turning on the high side (pull-up) FET of the inverting driver is charged to the full supply voltage using an active charging FET, instead of using a diode or diode-connected FET in a conventional bootstrapping driver. The gate voltage of the active charging FET is bootstrapped to a voltage higher than supply voltage by a second bootstrap capacitor that connects to the inverting driver input, which is at a logic high. The second bootstrap capacitor is charged by an additional diode or diode-connected FET connected to the supply voltage when the inverting driver input is a logic low.

Active bootstrapping drivers

A cross-coupled differential activated latch circuit with circuitry comprising a plurality of n-FETs and inverters that can be implemented completely in GaN. The circuitry prevents the digital latched values on the outputs of the latch from changing unless the digital input values on the inputs are different, thus preventing common-mode voltage on the inputs from corrupting the stored latch values.

Differential activated latch for GaN based level shifter

An enhancement mode GaN FET based gate driver circuit including an active pre-driver to drive a high-slew rate, high current output stage GaN FET. Due to the active driver current from the pre-driver, the output stage pull-up FET can turn on faster as compared to a pre-driver that utilizes a passive pull-up load. The active pre-driver must provide a voltage to drive the gate of the output stage pull-up FET which is higher than the normal supply voltage to enable the maximum output level of the driver FET to approach the normal supply voltage. A feedback circuit is included in the active pre-driver to avoid the need for two supply voltages.

GaN driver using active pre-driver with feedback

A laser-diode driver for Lidar applications with an output stage comprised of two enhancement mode GaN FETs. The output stage includes a driver GaN FET in a traditional common-source configuration, with the drain connected to the cathode of a laser diode and the source connected to ground. The gate of the driver GaN FET is driven by the source of the second, substantially smaller GaN FET in a source-follower configuration, rather than being driven directly by a pre-driver. The source-follower GaN FET has its drain connected to the drain of the common-source driver GaN FET, similar to a Darlington connection used in bipolar devices. The input drive signal from the pre-driver is applied at the gate of the source-follower GaN FET. The current required to turn on the driver GaN FET is thereby drawn from a main power supply through the laser diode, rather than from the power supply for the pre-driver, improving overall current efficiency.

GaN laser diode drive FET with gate current reuse

A cascaded bootstrapping gate driver configured to provide quick turn-on of a high side power FET and low static current consumption. The cascaded bootstrapping gate driver includes an initial bootstrapping stage with a resistor to decrease static current consumption during transistor turn-off. A secondary bootstrapping stage is driven by the initial bootstrapping stage and includes a GaN FET transistor with a low on resistance in place of the resistor. The source terminal of the GaN FET transistor provides a gate driving voltage to the high side power switch FET. The low on-resistance of the GaN FET transistor provides quick turn-on of the high side power FET. Transistors in the cascaded bootstrapping gate driver are preferably enhancement mode GaN FETs and may be integrated into a single semiconductor die.

Cascaded bootstrapping GaN power switch and driver

A circuit for providing an adjustable output driver current for use in LiDAR or other similar GaN driver applications. The circuit creates an appropriate gate-to-source voltage, V, for a high-current GaN driver FET to obtain a desired, high slew-rate driver current, I. An externally provided reference current is used to create the required Vfor the driver FET, which is stored on an external capacitor. The value of the capacitor far exceeds the relatively low input-capacitance of the GaN driver FET. When a pulse Iof desired value is needed, the voltage on the capacitor is impinged upon the gate of the driver FET, thereby creating the desired I. The reference charging circuit replenishes any charge lost on the capacitor, so that the same desired Ican be obtained on the next command pulse.

GaN based adjustable driver current circuit

A direct-coupled level shifter to level shift a ground referenced input logic signal to an output logic signal that can have either a positive or negative reference. The level shifter includes two level shift drivers, each of which includes a positive level shift driver and a negative level shift driver. The positive level shift drivers operate when the reference of the latch is above ground and turn off when the reference is below ground. Similarly, the negative level shift drivers operate when the reference is below ground and turn off when the reference is above ground. The output logic signal is based on the output from the positive level shift driver receiving the input signal and the output from the negative level shift driver receiving an inverse of the input signal. The inverse of the output logic signal is based on the output from the positive level shift driver receiving an inverse of the input signal and the output from the negative level shift driver receiving the input signal.

Level shifter in half bridge GaN driver applications

A driver shutdown circuit configured to trigger driver shutdown based on the magnitude and duration of the driving current. A first GaN FET is connected to a second GaN FET and an input node and generates a discharging current proportional to the driving current. The discharging current is drawn from a timer capacitor through the first and second GaN FETs. The second GaN FET receives a control signal and stops flow of the discharging current in between driver pulses so a pre-charger circuit can recharge the timer capacitor to a particular voltage. The discharging current drains the timer capacitor, and a shutdown signal generator outputs a shutdown signal to the driver in response to the voltage on the timer capacitor decreasing below a triggering voltage.

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Fullerton, CA, United States of America

Edward Lee