Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Avago Technologies General IP (singapore) Pte. Ltd.

Edward Law

Sam Ziqun Zhao

Rezaur Rahman Khan

Kevin (Kunzhong) Hu

Chonghua Zhong

Marc Papageorge

Pieter Vorenkamp

Reza-ur Rahman Khan

Liming Tsau

Andy Brotman

Sam Komarapalayam Karikalan

Sampath Komarapalayam Karikalan

Namhoon Kim

Kunzhong Hu

Zhihui Wang

Fan Yeung

Neal Andrew Kistler

Edmund Law

Ming Wang Sze

Galen Kirkpatrick

Reza Khan

Raymond (Kwok Cheung) Tsang

Kunzhong (Kevin) Hu

Reaz-ur Rahman Khan

Boon Leong Tan

Jin Seong Choi

An integrated circuit die includes a metal layer, a first passivation layer disposed above the metal layer, an aluminum containing redistribution layer disposed above the first passivation layer, an under bump metallization layer, and a redistribution layer plug. The redistribution layer plug is coupled to the metal layer and disposed in a via in the first passivation layer. The under bump metallization layer is coupled to the aluminum containing redistribution layer above the first passivation layer at a distance from the redistribution layer plug.

Redistribution metal and under bump metal interconnect structures and method

Semiconductor devices and manufacturing methods are provided for using a Recon interposer that provides a high density interface between the active semiconductor die and the semiconductor substrate and also provides the pitch fan-out. For example, a circuit assembly includes a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps. The circuit assembly further includes an oxide layer disposed on the silicon pad layer and an interposer dielectric layer disposed on the oxide layer. The interposer dielectric layer includes a plurality of routing traces that connect a top surface of the redistribution layer to a bottom surface of the interposer dielectric layer. The circuit assembly further includes an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps and an encapsulating material encapsulating at least a portion of the silicon pad layer, the oxide layer, the interposer dielectric layer, and the IC die to provide structural support for the circuit assembly.

Thin recon interposer package without TSV for fine input/output pitch fan-out

Inductors are fabricated in core layers according to a predefined semiconductor package manufacturing process rules. The inductors provide an embedded substrate trace inductor solution. The inductors may be part of an on-chip voltage regulator or any other circuit design. The inductors provide a core spiral structure to help increase inductance, particularly using magnetic field coupling between inductors. The core layers provide thicker and heavier conductive segments for the inductors, particularly as compared to inductors fabricated in build-up layers according to the semiconductor package manufacturing process rules.

Embedded substrate core spiral inductor

A 3-dimensional (3-D) magnetic core device includes a substrate, a first magnetic shell formed on the substrate, and a first group of conductive traces embedded in a first insulator layer formed on the first magnetic shell. A magnetic core plane is formed on the first insulator layer, and a second group of conductive traces are embedded in a second insulator layer formed on the magnetic core plane. A second magnetic shell is formed on the second insulator layer, and the first and second group of conductive traces are conductively coupled by using conductive vias.

Magnetic-core three-dimensional (3D) inductors and packaging integration

An integrated circuit (IC) device is provided. The IC device includes an IC die having opposing first and second surfaces, a carrier coupled to the first surface of the IC die, a laminate coupled to the carrier and the second surface of the IC die, and a trace located on a surface of the laminate and electrically coupled to a bond pad located on the second surface of the IC die. The trace is configured to couple the bond pad to a circuit board.

Thermal enhanced package using embedded substrate

A semiconductor package includes a semiconductor unit containing an active circuitry layer. The semiconductor package also includes a plurality of bonding pads on the active circuitry layer, which are configured to be connected to corresponding external conductive connectors. The semiconductor package also includes a protective sealant coating filling grooved edges of the active circuitry layer. The protective sealant coating contains an exterior wafer-singulated surface.

Semiconductor border protection sealant

An integrated circuit includes a monitoring circuit and a monitored circuit connected with the monitoring circuit. The monitoring circuit is operable to determine during fabrication if a resistance of a connection between an in-fab redistribution layer connector and a post-fab redistribution layer connector exceeds a threshold.

Wafer level package resistance monitor scheme

There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Fabricating a wafer level semiconductor package having a pre-formed dielectric layer

Wafer level semiconductor package

Embodiments described herein provide a method of manufacturing integrated circuit (IC) devices. The method includes coupling a first surface of a first intermediate substrate to a first surface of a second intermediate substrate, forming a first plurality of patterned metal layers on a second surface of the first intermediate substrate to form a first substrate and a second plurality of patterned metal layers on a second surface of the second intermediate substrate to form a second substrate, and separating the first and second substrates. Each of the first substrate and the second substrate is configured to facilitate electrical interconnection between a respective IC die and a respective printed circuit board (PCB).

Method and apparatuses for integrated circuit substrate manufacture

In one embodiment, a method for assembling a ball grid array (BGA) package is provided. The method includes providing a stiffener that has opposing first and second surfaces, wherein the first surface is capable of mounting an integrated circuit (IC) die in a central area and forming a pattern in at least a portion of the first surface to enhance the adhesiveness of an encapsulant material to the first surface.

Thermally and electrically enhanced ball grid array package

Method of fabricating a wafer level semiconductor package having a pre-formed dielectric layer

Embodiments for multi-chip and multi-substrate reconstitution based packaging are provided. Example packages are formed using substrates from a reconstitution. substrate panel or strip. The reconstitution substrate panel or strip may include known good substrates of same or different material types and/or same of different layer counts and sizes. As such, different combinations of reconstitution substrates and chips can be used within the same package, thereby allowing substrate customization according to semiconductor chip block(s) and types contained in the package.

Growing community of inventors

Ladera Ranch, CA, United States of America

Edward Law