Analog Devices,inc.

Edward L Wolfe

John Albert Geen

William Albert Clark

Steven J Sherman

William A Krieger

Vineet Kumar

David F Beigel

Andrew H Olney

Stephen T English

Detecting and/or mitigating the presence of particle contaminants in a MEMS device involves converting benign areas in which particles might become trapped undetectably by electric fields during test to field-free regions by extending otherwise non-functional conductive shield and gate layers and placing the same electrical potential on the conductive shield and gate layers. Particle contaminants can then be moved into detection locations remote from the potential trap areas and having particle detection structures by providing some mechanical disturbance.

Detection and mitigation of particle contaminants in MEMS devices

Detecting and/or mitigating the presence of particle contaminants in a MEMS device involves including MEMS structures that in normal operation are robust against the presence of particles but which can be made sensitive to that presence during a test mode prior to use, e.g., by switching the impedance of sensitive structures between an exceptionally sensitive condition during test and a normal sensitivity during operation; surrounding sensitive nodes with guard elements that are at the same potential as those nodes during operation, thereby offering protection against bridging particles, but are at a very different potential during test and reveal the particles by their resulting leakage currents; extending the sensitive nodes to interdigitate with or otherwise extend adjacent to the guard structures, which neither contribute to nor detract from the device operation but cover otherwise open areas with detection means during test; and/or converting benign areas in which particles might become trapped undetectably by electric fields during test to field-free regions by extending otherwise non-functional conductive layers so that the particles can then be moved into detection locations by providing some mechanical disturbance.

An apparatus and method for protecting semiconductor switching devices from damage due to electrostatic discharge is provided. The apparatus detects the occurrence of an ESD event, and turns the switching circuit to an operating state in which electrostatic charge is dissipated through the switching circuit. In embodiments of the invention, the switching circuit is a CMOS inverter circuit and the apparatus includes a PMOS transistor that upon occurrence of an ESD event couples an output of the inverter circuit to ground to discharge the electrostatic charge.

Electrostatic discharge protection circuit for protecting CMOS

A diode-connected transistor device for IC protection against electrostatic discharge (ESD) that functions as a transistor in the active region during an ESD event. The device cell includes an annular collector at the outer reaches of the cell, a circular base diffusion concentric with the collector, and an annular emitter near the outer edge of the base. The base and emitter regions are connected together by metallization external to the transistor cell. With the base contact enclosed by the annular emitter, during an ESD spike the initial reverse bias current flow is from the collector, under the emitter diffusion and out of the base contact. Eventually, as the magnitude of the ESD spike increases, the reverse biased current becomes sufficient to locally forward bias the base-emitter junction changing the primary ESD current path from collector to base, to collector to emitter, thus lowering the ESD current density in the active base-collector junction. Hence, the active emitter area is significantly increased with only a small increase in transistor area, resulting in reduced power density and joule heating, and increased overall ESD tolerance without significant change in parasitic capacitance.

Integrated circuit with diode-connected transistor for reducing ESD

An electrostatic discharge (ESD) protection circuit formed on a semiconductor substrate includes a first stage clamping circuit and a second stage clamping circuit separated by a dissipative circuit. The first and second stage clamping circuits are designed to absorb and dissipate the high and low energy ESD, respectively. The first clamping circuit has a self-regulated current mechanism capable of diverting the electrical current generated by an ESD from a high current density region to a low current density region within the semiconductor substrate, and simultaneously lowers the ESD induced voltage for safe protection.

Electrostatic discharge protection circuit

Differentially-connected pairs of JFETs on an IC chip are protected from ESD events by connecting respective discharge control resistors to the drains of the JFETs in such a manner as to be in series with any flow of current through either JFET.

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North Andover, MA, United States of America

Edward L Wolfe