Intel Corporation

Edward L Solari

Dawson L Yee

Subbarao S Vanka

Thomas A Heckenberg

An execution speed controller for controlling the effective processing rate of a microprocessor including an internal cache memory. In one embodiment, the execution speed controller monitors the activities of the microprocessor to determine when it is executing a section of code whose execution should be slowed. When such a determination is made, the execution speed controller periodically asserts at least one control input to the microprocessor. This periodically prevents the microprocessor from accessing the main memory and the internal cache memory, thereby slowing microprocessor execution. In this embodiment, only those software applications requiring slow down are effected. Newer software applications may not require this mode and may run at full speed. An alternate embodiment that does not require a triggering event is also described. In this embodiment, execution of all software applications is slowed down. This is referred to as the 'compatibility' mode.

Method of slowing down code execution in a microprocessor including an

A computer system has a dynamically adjustable speed bus. The dynamic speed bus system decreases the length of the bus cycle accesses required for fast peripherals; but, maintains normal (longer) length bus cycles for slower peripherals. Circuitry is provided to decrease the bus cycle length by increasing the clock frequency to the bus controller which controls the bus. When accessing peripherals that can support only normal length bus cycles, the circuitry of the present invention drives the bus controller with the normal lower clock frequency. When accessing faster peripherals, a higher clock frequency is generated such that the waveform transitions smoothly between the low and high bus frequencies. The dynamic speed bus circuitry of the present invention is divided into two logic sections: 1) a decode section and 2) a clock generation section. The decode section identifies faster peripherals that are compatible with shorter bus cycles.

Apparatus using a state machine for generating selectable clock

A method and apparatus for minimizing processor idle time resulting from the transfer of data between the processor and a resource. An intelligent First In First Out (FIFO) queuing scheme provides a basis for the transfer of data between a host bus and a system bus or between a bus and a resource. The FIFO posts write requests and provides an acknowledgement back to an originating resource on the host bus that the write request has been received. This acknowledgement enables the processor to continue processing. The FIFO further provides for detection of conditions where posted information may be processed out of First In First Out order and conditions where FIFO registers may be read from or data fields overwritten. This capability additionally minimizes idle time by reducing the number of posted items that need to be written to a resource during a read cycle to that resource.

Method and apparatus for priority selection of commands

An improved method of supporting service requests in certain bus architectures is disclosed. According to the presently invented method, the source, instead of using its own arbitration number, uses the arbitration number of the destination when performing an interrupt or DMA request. The destination then recognizes that it has been granted bus ownership, even though it was not arbitrating for the bus originally. The destination can therefore immediately assume that a request has occurred and immediately thereafter begin its request service routine.

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Monmouth, OR, United States of America

Edward L Solari