Nvidia Corporation

Creative Technology Corporation

Mellanox Technologies, Ltd.

Edward L Riegelsberger

Jyotirmaya Swain

Utpal Barman

Ziyad Sami Hakura

Stephen Donald Lew

John M Danskin

Jason M Musicer

Sagheer Ahmad

Laurent Rene Moll

Brian K Langendorf

Brad W Simeral

Martin Walsh

Yuval Itkin

Paul Gyugyi

Roman Surgutchik

Stephen Holmes

Robert William Chapman

Tony Yuhsiang Cheng

Ahmad Atamli

Micah S Stroud

Adarsh Kalliat

Raji Cherian

Varun Sampath

Nadir Muhammad Khan

Embodiments of the present disclosure are directed to efficient processes for recovering a hardware device in a computing system. Generally speaking, embodiments of the present disclosure include a two-part device recovery process. In a first part of the two-part process, an initial firmware image can be provided to the recovery device over a first, slower communication bus of the computing system. This initial image can provide the core for the device to communicate using a second, faster communications by of the computing system. A second part of the two-part process can then take place utilizing the second, faster communication bus.

Efficient device recovery

A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.

Training, power-gating, and dynamic frequency changing of a memory controller

Embodiments of the invention provide a policy-based audio system. The system includes a sound application protocol interface, a configuration module and a speaker driver. The sound application protocol interface receives a set of sound samples generated by an application or event. The configuration module retrieves a first group of one or more parameters, rules and priorities applicable to the application or event. The speaker driver produces an audio output by processing the set of sound samples as a function of the group of one or more configuration parameters, rules and priorities.

System and method for generating policy-based audio

According to an aspect of the present invention, one of multiple clock signals of different relative phases is selected based on a desired delay magnitude, and the digital values received on an input signal are then synchronized to an edge ('first edge') of the selected clock signal to provide the digital values with the desired delay magnitude. In an embodiment, the selected clock signal can be delayed by a fine value (less than the minimum phase difference of the multiple clock signals) to provide a wide span of desired delays. An aspect of the invention provides for a synchronization circuit with reduced latency and which is substantially invariant to process, voltage and temperature (PVT) changes.

Programmable delay circuit providing for a wide span of delays

Methods, circuits, and apparatus for reducing memory bandwidth used by a graphics processor. Uncompressed tiles are read from a display buffer portion of a graphics memory and received by an encoder. The uncompressed tiles are compressed and written back to the graphics memory. When a tile is needed again before it has been modified, the compressed version is read from memory, uncompressed, and displayed. To reduce the number of unnecessary writes of compressed tiles to memory, a tile is only written to memory if it has remained static for some number of refresh cycles. Also, to prevent a large number of compressed tiles being written to the display buffer in one refresh cycle, the encoder can be throttled after a number of tiles have been written. Validity information can be stored for use by a CRTC. If a tile is updated, the validity information is updated such that invalid compressed data is not read from memory and displayed.

Screen compression

Read leveling of memory units designed to receive access requests in a sequential chained topology writing a data pattern to the memory array. In an embodiment, a memory controller first writes a desired pattern into the memory array of a memory unit and then iteratively determines the accurate calibrated delay by setting a compensation delay to a test value, reading a data portion from the memory array based on the test value for the compensation delay, comparing the data portion with an expected data, determining that the test value is a calibrated compensation delay for the memory unit if the data portion equals the expected value.

Read leveling of memory units designed to receive access requests in a sequential chained topology

A memory controller provided according to an aspect of the present invention uses a slower clock signal during write leveling compared to when performing write operations thereafter. Due to such use of a slower clock signal, the various desired delays can be determined accurately and/or easily. In an embodiment, the frequency of the slower clock signal is determined based on the maximum fly-by delay (generally the delay between sending of a signal on the shared sequential path and the receipt at the memory unit in the sequence) that may be present in the memory system. For example, if the fly by delay can be M (an integer) times the time period of the clock signal during normal write operations, the slower clock signal may have a time period of M times that of the clock signal during write operation.

Write leveling of memory units designed to receive access requests in a sequential chained topology

A system has a plurality of different clients. Each client generates a report signal indicative of a current latency tolerance associated with a performance state. A controller dynamically determines a power down level having a minimum power consumption capable of supporting the system latency of the configuration state of the clients.

Apparatus, method, and system for dynamically selecting power down level

A method for adjusting a time delay between a first audio signal and a second audio signal is disclosed. The method includes generating the first audio signal from a buffer as a first data stream and generating the second audio signal from the buffer as a second data stream after an initial time delay. The method further includes receiving the first data stream at a first sample rate converter at a first consumption rate and generating a first output data stream at an output sample rate. The second data stream is received at a second sample rate converter at a second consumption rate and the second sample rate converter generates a second output data stream at the output sample rate. One of the first and second consumption rates are changed so that the time delay between the first and second output data streams is adjusted over time from the initial time delay. A system for adjusting the time delay between a first audio signal and a second audio signal is also disclosed.

System and method for adjusting delay of an audio signal

An audio rendering system and method are disclosed. The audio rendering system generally comprises front and rear signal modifiers configured to receive a plurality of audio signals representing a plurality of sources of aural information and location information representing apparent location for the source of said aural information. A gain is applied to the signals representative of the location information. A front signal modifier includes a plurality of head-related transfer functions filters and a rear signal modifier includes a plurality of filters configured to approximate head-related transfer function filters. The system further includes front speakers comprising a left front speaker and right front speaker configured to receive signals from the front signal modifier and generate a signal to a listener. At least one rear speaker is configured to receive signals from the rear signal modifier and generate a signal to the listener to offset frontward bias created by the front speakers. The gains applied to the signal are calculated to produce generally equal perceived energy from each of the front and rear speakers.

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Fremont, CA, United States of America

Edward L Riegelsberger