Interdigital Technology Corporation

Basil Leaf Technologies, LLC

Interdigital Technology Corpoartion

Vid Scale, Inc.

Edward L Hepler

Alexander Reznik

Michael F Starsinic

David S Bass

William C Hackett

Peter Bohnhoff

Jan Meyer

Douglas R Castor

John David Kaewell, Jr

Stephen E Terry

Guodong Zhang

Ariela Zeira

Liangping Ma

Michael J Koch

Steven Ferrante

Peter Shaomin Wang

Kamel M Shaheen

James M Miller

Ravikumar V Pragada

Robert G Gazda

Timothy Berghuis

George W McClellan

Joseph Gredone

Jung-Lin Pan

Hang Liu

Paul L Russell, Jr

Clyde N Robbins

Weimin Liu

Zhuorong Deng

Zhifeng Chen

Avi Rapaport

Renuka Racha

Richard P Gorman

Alan M Levi

Harry Seth Smith

George C Harris

Binish P Desai

Basil M Harris

Jung Lin Pan

Eun Ryu

Timothy Berghius

Constantine F Harris

Philip J Charron

Julia D Harris

Andrew D Singer

Alexander Reznick

Chris Wallace

Automated camera-based optical assessment involves color assessment of a physical object using conventional and inexpensive computer hardware such as a smartphone. A specially-configured test card includes a body supporting a reagent pad configured to change to an expected color in response to an enzymatic reaction, and an imaging key adjacent the reagent pad. The imaging key includes color fields including at least one field of the expected color. The hardware captures an image of the test card, and processes the image to identify the reagent pad and color fields, to process a brightness calibration target, to determine color values for the reagent pad and color fields, to calibrate the color values as a function of brightness and/or color by comparison to the brightness and color calibration targets, and to identify a color field most closely matching the reagent pad's color to determine a corresponding test result.

Automated camera-based optical assessment system and method

A non-invasive blood sensor includes a body configured to mate with a tissue surface; a blue light source disposed on the sensor body; and a photodetector disposed on the sensor body at a suitable position for capturing light emanating from the tissue surface after emission from the blue light source, e.g., by one of: transmission, reflection, and transflection. The sensor bodies may further include a green, a red and/or an infrared light source. The light source(s) and photodetector(s) may be supported on a support structure configured to register with a corresponding portion of human anatomy in a predetermined fashion, and support the light sources and photodetectors in a defined spatial relationship. The sensor or an integrated meter may include a controller programmed to receive signals from the photodetector and calculate blood glucose value as function of the signals received from the photodetector after emission by the light source(s).

Non-invasive blood glucose sensor

A protocol engine (PE) for processing data within a protocol stack in a wireless transmit/receive unit (WTRU) is disclosed. The protocol stack executes decision and control operations. The data processing and re-formatting which was performed in a conventional protocol stack is removed from the protocol stack and performed by the PE. The protocol stack issues a control word for processing data and the PE processes the data based on the control word. Preferably, the WTRU includes a shared memory and a second memory. The shared memory is used as a data block place holder to transfer the data amongst processing entities. For transmit processing, the PE retrieves source data from the second memory and processes the data while moving the data to the shared memory based on the control word. For receive processing, the PE retrieves received data from the shared memory and processes it while moving the data to the second memory.

Protocol engine for processing data in a wireless transmit/receive unit

A method for increasing data rate in wireless communications includes selectively activating a plurality of hardware accelerators, and performing, using the hardware accelerators, data processing for modem data based on parameters received from a processor.

UMTS FDD modem optimized for high data rate applications

A method for processing enhanced dedicated channel (E-DCH) data in a wireless transmit/receive unit (WTRU) includes sending two messages. A first message is sent from a physical layer to a medium access control (MAC) layer, and triggers MAC layer processing of E-DCH data. A second message is sent from the MAC layer to the physical layer, and enables the physical layer to compute control parameters for physical layer processing of the E-DCH data before the MAC layer processing of the E-DCH data is completed.

Method and apparatus for efficient operation of an enhanced dedicated channel

Methods and apparatus for performing error correction of data bits are disclosed. A forward metric calculation may be performed during a first window to generate a first group of calculated data. The first group of calculated data from the forward calculation may be stored in a memory location. A forward metric calculation may be performed during a second window to generate a second group of calculated data. The first group of calculated data may be read from the memory location and the second group of calculated data may be stored in the same memory location. The first group of calculated data may be used to calculate reverse metrics.

Pipeline architecture for maximum a posteriori (MAP) decoders

A method and apparatus for optimization of a modem for high data rate applications comprise a plurality of hardware accelerators which are configured to perform data processing functions, wherein the hardware accelerators are parameterized, a processor is configured to selectively activate accelerators according to the desired function to conserve power requirements and a shared memory configured for communication between the plurality of hardware accelerators.

A data processing system ciphers and transfers data between a first memory unit and a second memory unit, such as, for example, between a share memory architecture (SMA) static random access memory (SRAM) and a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The system includes a ciphering engine and a data-mover controller. The data-mover controller includes at least one register having a field that specifies whether or not the transferred data should be ciphered. If the field specifies that the transferred data should be ciphered, the field also specifies the type of ciphering that is to be performed, such as a third generation partnership project (3GPP) standardized confidentially cipher algorithm 'f' or integrity cipher algorithm 'f

Data-mover controller with plural registers for supporting ciphering operations

A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Software parameterizable control blocks for use in physical layer processing

A hardware accelerator includes a first buffer, a second buffer, address generator(s), a translation read-only memory (ROM), a cyclic redundancy check (CRC) generator, a convolutional encoder and a controller. The first and second buffers store information bits. The address generator(s) generate(s) an address for accessing the first buffer, the second buffer and a shared memory architecture (SMA). The translation ROM is used in generating a translated address for accessing the first buffer and the second buffer. The controller sets parameters for the CRC generator, the convolutional encoder and the address generator, and performs a predefined sequence of control commands for channel processing, such as reordering, block coding, parity tailing, puncturing, convolutional encoding, and interleaving, on the information bits by manipulating the information bits while moving the information bits among the first buffer, the second buffer, the SMA, the CRC generator, and the convolutional encoder.

Symbol rate hardware accelerator

A method and apparatus for efficient operation of an enhanced dedicated channel (E-DCH) are disclosed. A physical layer processing includes computation of various control parameters followed by actual processing of the data to be transmitted. In accordance with the present invention, the computation of the control parameters is performed asynchronously from the associated data operation. A medium access control (MAC) layer provides information needed for computation of the control parameters to the physical layer as early as possible, while the data is being processed in parallel. The provided data includes a hybrid automatic repeat request (H-ARQ) profile, a transport block size, power offset, or the like. By sending this data to the physical layer before MAC-e processing is complete, the latency constraint can be significantly relaxed.

The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is written to the same memory location. The calculations can be reversed, reverse metrics being calculated first, followed by reverse metric calculations. Although this architecture as developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.

A system for generating pseudorandom codes using a register which contains an identification of the code tree leg of the desired code and a counter which outputs a successive binary sequence. The output from the counter is bit-by-bit ANDed with the output of the register, and those outputs are XORed together to output a single bit. As the counter is sequenced, each count results in a different bit that is output from the XOR gate, resulting in the desired code.

System for generating pseudorandom sequences

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Malvern, PA, United States of America

Edward L Hepler