Intermolecular, Inc.

Elpida Memory, Inc.

Globalfoundries Inc.

Edward L Haywood

Sandra Guy Malhotra

Hanhong Chen

Pragati Kumar

Imran Hashim

Sunil Shanker

Hiroyuki Ode

Xiangxin Rui

Wim Deweerd

Nobi Fuchigami

Tony P Chiang

Indranil De

Prashant B Phatak

Monica Sawkar Mathur

Nobumichi Fuchigami

Gerald Donald Richardson

Paul Raymond Besser

Hoon Sik Kim

Kisik Choi

Albert Sanghyup Lee

Richard Endo

Salil Mujumdar

ALD of HfAlCfilms using hafnium chloride (HfCl) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfClpulse time allows for control of the Al % incorporation in the HfAlCfilm in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfAlCwork function layer coupled with ALD deposited HfOhigh-k gate dielectric layers was quantified to be mid-gap at &#x2dc;4.6 eV. Thus, HfAlCis a promising metal gate work function material allowing for the tuning of device threshold voltages (V) for anticipated multi-Vintegrated circuit (IC) devices.

Atomic layer deposition of HfAlC as a metal gate workfunction material in MOS devices

Embodiments of the present invention provide vapor deposition tools. In one example, a vapor deposition tool includes housing. A substrate support is positioned within the housing and configured to support a substrate. A backing plate is positioned above the substrate support. A showerhead is positioned between the substrate support and the backing plate and has a plurality of openings therethrough. A fluid trap member is positioned around a periphery of the showerhead. A fluid trap member actuator is coupled to the fluid trap member and configured to move the fluid trap member between first and second positions relative to the backing plate.

Vapor based processing system with purge mode

This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

Yttrium and titanium high-K dielectric film

Yttrium and titanium high-k dielectric films

Determining an unknown step coverage of a thin film deposited on a 3D wafer includes exposing a planar wafer comprising a first film deposited thereon to X-ray radiation to create first fluorescent radiation; detecting the first fluorescent radiation; measuring a number of XRF counts on the planar wafer; creating an XRF model of the planar wafer; providing a portion of the 3D wafer comprising troughs and a second film deposited thereon; determining a multiplier factor between the portion of the 3D wafer and the planar wafer; exposing the portion of the 3D wafer to X-ray radiation to create second fluorescent radiation; detecting the second fluorescent radiation; measuring a number of XRF counts on the portion of the 3D wafer; calculating a step coverage of the portion of the 3D wafer; and determining a uniformity of the 3D wafer based on the step coverage of the portion of the 3D wafer.

System and method for step coverage measurement

A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive metal oxide formed using a high temperature, low pressure ALD process. The high temperature ALD process results in a layer with enhanced crystallinity, higher density, reduced shrinkage, and lower carbon contamination. The high temperature ALD process can be used for either or both the bottom electrode and the top electrode layers.

High temperature ALD process of metal oxide for DRAM applications

High temperature ALD process for metal oxide for DRAM applications

This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i.e., to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures.

Methods for forming high-K crystalline films and related devices

This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal ('MIM') stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiOdielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiOdielectric and reduce interface states between TiOand electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.

Titanium based high-K dielectric films

A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.

Integration of non-noble DRAM electrode

A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 &#x3bc;&#x3a9; cm. Advantageously, the electrode materials are conductive molybdenum oxide.

Enhanced non-noble electrode layers for DRAM capacitor cell

A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 &#x3bc;&#x3a9;cm. Advantageously, the electrode materials are conductive molybdenum oxide.

Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.

Methods for depositing high-K dielectrics

In some embodiments of the present invention, methods are developed wherein a gas flow of an electron donating compound (EDC) is introduced in sequence with a precursor pulse and alters the deposition of the precursor material. In some embodiments, the EDC pulse is introduced sequentially with the precursor pulse with a purge step used to remove the non-adsorbed EDC from the process chamber before the precursor is introduced. In some embodiments, the EDC pulse is introduced using a vapor draw technique or a bubbler technique. In some embodiments, the EDC pulse is introduced in the same gas distribution manifold as the precursor pulse. In some embodiments, the EDC pulse is introduced in a separate gas distribution manifold from the precursor pulse.

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San Jose, CA, United States of America

Edward L Haywood