International Business Machines Corporation

Edward Kelley Evans

Roderick Michael West

Daniel Joseph Liguori

Jeanne P Bickford

Chin-Long Chen

William Eric Hall

Eric M Foster

Dennis E Franklin

Joseph W Yoder

Raymond J Rosner

Andrew S Wienick

David D Litten

Stephen B Barrett

David L Arlington

Stephen J Stratz

R Michael West

Peter Casavant

Hiroyuki Ando

Sean Horner

Andrew Anthony Long

A method and system for predicting manufacturing yield for a proposed integrated circuit The method includes: in the order recited: (a) providing a multiplicity of different integrated circuit library elements in a design database, each library element linked to a corresponding normalization factor in the design database; (b) selecting library elements from the design database to include in a proposed design for the integrated circuit; (c) generating an equivalent circuit count of the proposed design based on the normalization factors and a count of each different library element included in the proposed design; and (d) calculating a predicted manufacturing yield based on the equivalent circuit count, a predicted density of manufacturing defects and an area of the proposed integrated circuit chip.

Method for modeling integrated circuit yield

An access control function for an integrated system is provided which determines data access based on the master id of a requesting master within the system and the address of the data. The access control function can be inserted, for example, into the data transfer path between bus control logic and one or more slaves. In addition to determining whether to grant access to the data, the access control function can further qualify the access by selectively implementing encryption and decryption of data, again dependent on the data authorization level for the particular functional master initiating the request for data.

Control function employing a requesting master id and a data address to qualify data access within an integrated system

A graphics display subsystem providing internally timed time-varying properties of display attributes is provided. The graphics display subsystem comprises a display device for displaying consecutive image frames of pixels having a variable display property, and a circuit for transferring image frames to the display device. One or more pixels are selected when a display attribute associated with the one or more pixels is set in an attribute table. The circuit varies, during a selected time interval, the display property of the selected pixels being displayed on the display device. In preferred embodiments, the variable display property is either a stereo image display, an image brightness control, or an image-blending control.

Graphics display system and method for providing internally timed

A method and apparatus which produces a semitransparent cursor for a video display presenting simultaneous viewing access to both the cursor and the underlying image information. At the on-screen location of the cursor, the viewer is able to simultaneously view and distinguish between the cursor and the underlying graphical data. In one form, the method includes the steps of obtaining the red, green, and blue video pixel data for each pixel representing at least a portion of the cursor; halving the numerical value of each datum of red, green, and blue video pixel data; injecting a binary value into the most significant bit of each datum to obtain modified red, green, and blue video pixel data; and providing modified red, green, and blue video pixel data to a video display.

Method and apparatus for producing a semi-transparent cursor on a data

A graphics system comprising a format processor for receiving display data including pixel data and color-blending information for at least two (2) separate display layers, a color blender and color processors. The pixel data includes color information for the display layers. The color-blending information determines weighting factors for use in blending the colors of the display layers. The format processor outputs separate streams of pixel data, one for each display layer, as well as the weighting factors. Each stream of pixel data outputted by the processor is inputted into a corresponding color processor that assigns colors to a particular display layer according to the color information in the corresponding pixel data. The color blender blends the colors assigned to the display layers according to the weighting factors.

Graphics system and process for blending graphics display layers

The graphics display system comprises a data bus for transferring a set of application pixels, wherein a set consists of W number of blocks of data, and wherein each application pixel is M number of blocks. The graphics display system further comprises an address bus for transferring memory addresses, a graphics controller for outputting pixel data on the data bus at a rate of one set per memory clock cycle and for outputting one or more column addresses on the address bus for each set, and a graphics memory configured for a memory field size of N number of blocks such that an application pixel being stored is allocated N blocks. A set of application pixels is transferred over the data bus to the graphics memory, and, one or more column addresses are transferred over the address bus during the a memory clock cycle over the address bus. In addition, a row address is transferred to the graphics memory. Each block of the transferred set belongs to one of N/M groups of blocks, and each of these blocks are stored in the graphics memory in a memory field indicated by a transferred row and column address pair, wherein each group of blocks is stored at a different one of N/M number of column addresses for any given transferred set.

Method and system of updating graphics memory in a graphics display

A method and apparatus for a computer graphics system identifies the format of video pixel data in a data stream having a plurality of data formats including a first pixel data format and a second pixel data format, the second pixel data format being a YUV format. The method comprises the steps of (a) receiving pixel data; (b) selecting an output channel in response to at least one particular value of at least one bit of each received pixel datum wherein the particular value identifies the data format as either the first pixel data format or the YUV format; and (c) providing the pixel data to the selected output channel. Also provided is a circuit in a video graphics controller and a computer system having such circuit according to the method.

Method for identifying video pixel data format in a mixed format data

A programmable serializer comprising a multi-bit input port, a multi-bit output port, at least one multiplexer and at least one programmable address counter corresponding to the multiplexer for generating a sequence of multiplexer data input addresses that are inputted into the multiplexer address input. The multiplexer has an output connected to the multi-bit output port, an address input and a plurality of data input channels having addresses. Each data input channel is connected to a corresponding bit of the multi-bit input port. At least one data input channel is coupled to the multiplexer output when the corresponding address of the data input channel is applied to the address input. The programmable address counter receives and stores an initial address value, an address increment value and a count value and generates a sequence of addresses based on these values. The initial address value represents the multiplexer data channel that is to be initially coupled to the multiplexer output. The address increment value represents the increment that must be added to a current address in order to reach a next address. The count value represents the number of address that must be generated by the counter prior to restarting the sequence at the initial address value.

Programmable serializer using multiplexer and programmable address

A graphics display subsystem that allows rejection of double buffer display of pixel data in a graphics layer is provided. The subsystem has a memory containing a plurality of pixels represented by binary bits, wherein each pixel is divided into two or more sub-pixel fields, and wherein one or more bits of a particular sub-pixel field of a given pixel are set to a predetermined double buffer reject value when the given pixel corresponds to a single buffer display application. A double buffer reject circuit compares one or more bits of a double buffer sub-pixel field of a given pixel with a predetermined double buffer reject value to determine equality of the one or more bits and the predetermined value, wherein the given pixel is represented by binary bits and wherein the given pixel is divided into two or more sub-pixel fields including the double buffer sub-pixel field. The double buffer reject circuit receives a buffer select signal selecting one of the two or more sub-pixel fields of the given pixel to be accessed during a current display frame. In response, the double buffer reject circuit accesses the selected sub-pixel field of the given pixel when the buffer select signal does not select the double buffer sub-pixel field or when the buffer select signal selects the double buffer sub-pixel field and the comparison does not show equality, and further the double buffer reject circuit accesses one of the two or more sub-pixel fields of the given pixel that is not the double buffer sub-pixel field when the buffer select signal selects the double buffer sub-pixel field and the comparison shows equality. A digital-to-analog converter in communication with the double buffer reject circuit receives the pixel data contained in the sub-pixel field accessed by the double buffer reject circuit and converts the pixel data into analog video signals for driving a monitor display device.

Graphics display subsystem that allows per pixel double buffer display

An extended error code particularly applicable to a code that can correct any number of errors in one sub-field but can only detect the existence of any number of errors in two sub-fields. If the initial pass of the data through the error correction code indicates an uncorrected error, the data is complemented and restored in the memory and then reread. The retrieved data is recomplemented and again passed through the error correction code. If an uncorrected error persists, then a bit-by-bit comparision is performed between the originally read data and the retrieved complemented data to isolate the hard fails in the memory. The bits in the sub-field associated with the hard fail are then sequentially changed and then the changed data word is passed through the error correction code. A wrong combination is detected by the error correction code. The sequential changing continues until the bits in the sub-field associated with the hard fail match the originally stored data, in which case the error correction code can correct the remaining errors in the remaining sub-fields.

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Essex Junction, VT, United States of America

Edward Kelley Evans