Auspex Systems, Inc.

Edward John Row

Laurence B Boucher

William Michael Pitts

Stephen E Blightman

Clive M Philbrick

Peter K Craft

David A Higgen

Paul Lester Popelka

Richard A Walter

Lakshman Narayanaswamy

Tarun Kumar Tripathy

Daniel Murray Jones

Leslie Thomas McCutcheon

Amod Prabhakar Bodas

Donald Wayne Sterk

Murali Sundaramoorthy Repakula

Paul Brian Del Fante

A scalable computer system has an interconnect bus providing communication links among a host processor and one or more function-specific processors, including a network processor (NP) and a file storage processor (FSP). The host processor provides a single interface to network administrators for maintaining the system. A bi-endian conversion system is provided to minimize a need for translating between big and little endian data types generated by diverse processors. The NP shares a single memory image with other processors and has a buffer memory for buffering requests from the network interfaces. The buffer memory has one or more segments which are dynamically allocatable to different processors. The FSP has a metadata cache for maintaining information on data being cached in the NP buffer memory. The FSP also has a write cache for buffering file write operations directed at disks. Upon receiving requests for data from the NP, the FSP checks the metadata cache to see if a copy of the requested data has been cached in the NP buffer and, if the copy exists in the NP buffer, causing the NP with the data to respond to the request. The resulting scalable computer provides higher data availability, faster access to shared data, and reduced administrative costs via data consolidation.

Processing system with dynamically allocatable buffer memory

A file server architecture is disclosed, comprising as separate processors, a network controller unit, a file controller unit and a storage processor unit. These units incorporate their own processors, and operate in parallel with a local Unix host processor. All networks are connected to the network controller unit, which performs all protocol processing up through the NFS layer. The virtual file system is implemented in the file control unit, and the storage processor provides high-speed multiplexed access to an array of mass storage devices. The file controller unit control file information caching through its own local cache buffer, and controls disk data caching through a large system memory which is accessible on a bus by any of the processors.

Parallel I/O network file server architecture

Growing community of inventors

Mountain View, CA, United States of America

Edward John Row