Analog Devices International Unlimited Company

Analog Devices,inc.

Analog Devices Global

Analog Devices Global Unlimited Company

Edward John Coyne

David J Clarke

William Allan Lane

Alan J O'Donnell

David Aherne

Shaun Bradley

David M Boland

Patrick Martin McGuinness

Mark Forde

Colm Patrick Heffernan

Kevin B Manning

Michael A Looby

Thomas G O'Dwyer

Eamon Hynes

Seamus Paul Whiston

Stephen Denis Heffernan

Shane Patrick Geary

Alan Brannick

Breandán Pol Og Ó hAnnaidh

Nijun Wei

Paul Malachy Daly

Catriona Marie O'Sullivan

Shane Tooher

John P Meskell

Bernard Patrick Stenson

Donal McAuliffe

Andrew David Bain

Colin Gerard Lyden

Derek F Bowers

Laurence Brendan O'Sullivan

Brian Anthony Moane

John Twomey

Shane Geary

Eric Modica

Brian Sweeney

Breandán Pol Og ÓhAnnaidh

William Alan Lane

Donai P McAuliffe

Jagar Singh

Breandan Pol Og O Hannaidh

Patrick Martin Mcguinness

Seamus P Whiston

Donal P Mcauliffe

The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices including a metal-oxide-semiconductor (MOS) transistor and are configured for accelerating and monitoring degradation of the gate dielectric of the MOS transistor. In one aspect, a semiconductor device configured with gate dielectric monitoring capability comprises a metal-oxide-semiconductor (MOS) transistor including a source, a drain, a gate, and a backgate region formed in a semiconductor substrate. The semiconductor device additionally comprises a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the backgate region of the MOS transistor serves as the base of the BJT and is independently accessible for activating the BJT. The MOS transistor and the BJT are configured to be concurrently activated by biasing the backgate region independently from the source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the backgate region of the MOS transistor, where the first charge type is opposite charge type to channel current carriers.

Semiconductor device configured for gate dielectric monitoring

The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes.

Wearable device with energy harvesting

A JFET is provided with a very low gate current. In tests the excess gate current above the theoretical minimum current for a similarly sized reverse biased p-n junction was not observed. The JFET includes a lightly doped top gate and doped regions beneath the drain of the JFET.

Low gate current junction field effect transistor device architecture

The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

Lifetime indicator system

Spark gap structures for detection and protection against electrical overstress events

Exposure monitor device

A bipolar junction transistor is provided with an emitter structure that is positioned above the upper surface of the base region. The thickness of the emitter and the interfacial oxide thickness between the emitter and the base is configured to optimize a gain for a given type of transistor. A method of fabricating PNP and NPN transistors on the same substrate using a complementary bipolar fabrication process is provided. The method enables the emitter structure for the NPN transistor to be defined separately to that of the PNP transistor. This is achieved by epitaxially growing the emitter layer for the PNP transistor and growing the emitter layer for the NPN transistor in a thermal furnace.

Bipolar junction transistor, and a method of forming an emitter for a bipolar junction transistor

A modified structure of an n-channel lateral double-diffused metal oxide semiconductor (LDMOS) transistor is provided to suppress the rupturing of the gate-oxide which can occur during the operation of the LDMOS transistor. The LDMOS transistor comprises a dielectric isolation structure which physically isolates the region comprising a parasitic NPN transistor from the region generating a hole current due to weak-impact ionization, e.g., the extended drain region of the LDMOS transistor. According to an embodiment of the disclosure, this can be achieved using a vertical trench between the two regions. Further embodiments are also proposed to enable a reduction in the gain of the parasitic NPN transistor and in the backgate resistance in order to further improve the robustness of the LDMOS transistor.

High voltage double-diffused metal oxide semiconductor transistor with isolated parasitic bipolar junction transistor region

A bipolar junction transistor is provided with a multilayer collector structure. The layers of the collector are individually grown in separate epitaxial growth stages. For a PNP transistor, each layer, after it is grown, is doped with a p-type dopant in a dedicated implant stage. By providing separate epitaxial growth stages and separate dopant implant stages for each layer of the collector, the dopant concentration profile in the collector region can be better controlled to optimize the speed and breakdown voltage of a bipolar junction transistor.

Bipolar junction transistor, and a method of forming a collector for a bipolar junction transistor

A charge control structure is provided for a bipolar junction transistor to control the charge distribution in the depletion region extending into the bulk collector region when the collector-base junction is reverse-biased. The charge control structure comprises a lateral field plate above the upper surface of the collector and dielectrically isolated from the upper surface of the collector and a vertical field plate which is at a side of the collector and is dielectrically isolated from the side of the collector. The charge in the depletion region extending into the collector is coupled to the base as well as the field-plates in the charge-control structure, instead of only being coupled to the base of the bipolar junction transistor. In this way, a bipolar junction transistor is provided where the dependence of collector current on the collector-base voltage, also known as Early effect, can be reduced.

Bipolar junction transistor, and a method of forming a charge control structure for a bipolar junction transistor

Growing community of inventors

Athenry, Ireland

Edward John Coyne