Eastman-kodak Company

Other

Tandem Computers Incorporated

Edward J Weldon, Jr

Dennis G Howe

Hugh M Hilden

David Slepian

In a shift correction decoder which processes d,k-constrained RLL data that is encoded in accordance with a shift correction code whose symbols in GF(p) comprise modulo p reductions of cumulative sums of successive run symbols of the RLL data (where p is an odd prime), additive errors (i.e., drop-out and drop-in errors) in the received RLL data are corrected by relying in part on information pertaining to the sequence of the polarities of successive 1-bits in the received RLL data. The polarity information is used to either insert missing 1-bits (due to drop-outs) or delete spurious 1-bits (due to drop-ins) and specify to the shift correction decoder the location of an additive error as an erasure. Synchronization slips are corrected by pre-multiplying the received codeword polynomial by a factor which reduces to two the number of errors created by a single synchronization slip. GF(p) is selected such that p.ltoreq.k-d+ 1 and the minimum distance of the shift correction code is selected to be sufficient to enable correction of a limited number of shift errors, additive errors and synchronization slips within one received codeword.

Shift correction code system for correcting additive errors and

A method for coding/decoding ternary symbols to d,k-constrained binary runs in a way that (i) associates (codes) a number of ternary symbols with a lesser number of d,k-constrained binary runs and (ii) provides that an individual single-shift error in any of the received binary runs that constitute a binary data codeword will cause at most one ternary symbol to be in error in the associated (decoded) ternary symbol codeword. This method allows shift-correction codeword parity checks to be transmitted (i.e., transformed to a d,k-constrained channel data sequence) with increased efficiency, so that the required number of channel bits needed to represent the parity checks is decreased.

Shift-correction code rate-enhancing parity encoding/decoding

Channel encoded data (for example run length limited encoded data) is further encoded in accordance with a shift correction code prior to transmission. Upon reception, forward and backward shift errors present in the received channel encoded data are corrected by a shift correction decoder. The shift error correction is accomplished using a code, such as (for example) a BCH code over GF(p) or a negacyclic code, which treats each received symbol as a vector having p states. For a single shift error correction, p=3 and there are three states (forward shift, backward shift, no shift). In one embodiment, conventional error correction codewords which encode the user data may be interleaved within successive shift correction codewords prior to channel encoding, thereby enabling the error correction system to easily handle a high rate of randomly distributed shift errors (which otherwise would result in a high rate of short error bursts that exceed the capacity of the block error correction code).

Shift correcting code for channel encoded data

Interleaved cyclic error correction encoded binary data, of the type employed in the compact audio disk standard for example, in which the parity characters are located in the middle of a codeword, are encoded by a serial encoder to greatly increase the speed at which such data may be recorded. In the invention, the message characters are treated as two polynomials, a left-hand sub-codeword or message block representing the message characters to the left of the parity characters and a right-hand sub-codeword or message block representing the message characters to the right of the parity characters. The encoder of the invention has two parallel inputs which simultaneously receive the message characters of the right-hand and left-hand sub-codewords, respectively, each input receiving one character at a time in serial fashion. The encloder is a serial register in which each stage receives the sum of the contents of the previous stage and (a) the product of the current character of the left-hand sub-codeword multiplied by a respective coefficient of the code generator polynomial and (b) the product of the current character of the left-hand sub-codeword multiplied by a respective coefficient of the residue of an algebraic shift factor, whose degree is equal to the length of the cyclic error correction code minus the length of the sub-codeword, divided by the code generator polynomial.

High speed encoder for non-systematic codes

Simplified method and apparatus for performing integrated scrambling and encoding or descrambling and decoding of block code digital transmissions is disclosed. The method involves setting the scrambling length equal to an integer multiple of the block length, and then implementing a pseudorandom number sequence generator within the block length counter. The output of the pseudorandom number sequence generator is then logically combined with the incoming data to provide scrambled data, simplifying the complexity of the encoder or decoder significantly.

Integrated scrambler-encoder using PN sequence generator

Method and apparatus for determining pitch by establishing the fundamental period of an incoming acoustic wave and comparing this fundamental period with the period of certain standard pre-established tones. The name of the standard tone with period closest to the measured fundamental period of the incoming wave is indicated and displayed. Also displayed is an indication of the degree and direction of any deviation between the pitch of the incoming wave and that of the displayed standard tone.

Growing community of inventors

Honolulu, HI, United States of America

Edward J Weldon, Jr