Sige Semiconductor, Inc.

Sige Semiconductor (u.s.), Corp.

Edward J W Whittaker

Christopher Andrew Zelley

A collector boost circuit is disclosed for providing a first voltage in a first mode of operation to a power amplifier, and a second voltage in a second mode of operation to the power amplifier. The collector boost circuit uses a switch and an indicator signal for triggering the switch between the first and the second mode of operation. The second voltage is a boosted voltage greater than the first voltage and is provided during peak excursions through a boost capacitor.

Integrated implementation of a collector boost scheme and method therefor

A low voltage wide ratio current mirror circuit comprises an n times current mirror having an input port for receiving an input current and an m times current mirror coupled in series to the n times current mirror for resulting in an output current of (N*M the input current) being provided to a load where at least one of N and M is other than 1. The circuit provides precision in output current for use with a low voltage power amplifier without incurring an overhead of quiescent current. The low voltage wide ratio current mirror circuit in accordance with a second embodiment of the invention includes a voltage swing reduction circuit in order to provide increased stability thereto. In additional embodiments of the invention, the load is a differential amplification stage for providing differential amplification to differential RF input signals received at first and second RF input ports thereof.

Low voltage wide ratio current mirror

A dual output voltage regulator circuit is disclosed. The output voltage regulator has a first FET and a second FET. A current source responsive to the regulated output voltage provides a current drive to the gate of the first FET in a first mode of operation and to the gate of the second FET in a second mode of operation. Further, the circuit employs switches for switchably selecting between the first mode of operation and the second mode of operation.

Voltage regulator circuit with two or more output ports

A low dropout (LDO) PFET regulator circuit is disclosed for operating in two modes of operation. For higher supply voltage potentials the LDO PFET regulator circuit operates normally, as supply voltage potential drops, the LDO PFET regulator operates in a second mode of operation where a decision circuit determines whether to supply a first boost current thereto in order to compensate for the reduced transimpedance of the first PFET.

Fast low drop out (LDO) PFET regulator circuit

A power amplifier circuit is disclosed having a first amplification stage and a second amplification stage. The first amplification stage is biased using a controllable current source that provides a variable bias current thereto. A control circuit is provided for controlling the variable bias current in dependence upon the supply voltage and temperature of the power amplifier circuit. The control signal varies the variable bias current in dependence upon the supply voltage varying between first and second potential, where each potential supplies sufficient potential for operation of the power amplifier circuit.

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Bishops Stortford, United Kingdom

Edward J W Whittaker