International Business Machines Corporation

Edward J Tasillo

Michael A Gaynes

Mark Vincent Pierson

Ramesh R Kodnani

Allan O Johnson

Floyd W Olsen

Robert L Schaaf

A method for aligning a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate is arranged on a coverplate support. A first layer of a bonding material is applied to at least one of a first side of each of the tiles and a surface of the coverplate on which the tiles are to be secured. The tiles are arranged on the coverplate, such that the first layer of bonding material is arranged between the tiles and the coverplate. The tiles are connected to an alignment apparatus. The tiles are aligned relative to each other and the coverplate. The tiles are at least partially secured to the coverplate.

TFT panel alignment and attachment method and apparatus

A system for aligning and attaching together a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate loading station where a coverplate that the tiles are to be attached to is arranged on a coverplate support. A coverplate bonding material dispensing station where a bonding material for bonding the tiles to the coverplate is applied to a surface of the coverplate. A tile placement station where the tiles are arranged on the coverplate. A tile aligning and securing station where the tiles are aligned relative to each other and the coverplate by the tile aligner and where the tiles are at least partially bonded to the coverplate. A tile assembly bonding material dispensing station where a bonding material is applied to a surface of the tiles opposite the side that the coverplate is bonded to. A backplate placement station where a backplate is arranged on the tiles. A backplate aligning and securing station where the backplate is aligned with the tiles and the coverplate and at least partially secured to the tiles. A full bonding station where the tiles are fully bonded to the coverplate and the backplate.

A system for aligning and attaching together a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate loading station where a coverplate that the tiles are to be attached to is arranged on a coverplate support. A coverplate bonding material dispensing station where a bonding material for bonding the tiles to the coverplate is applied to a surface of the coverplate. A tile placement station where the tiles are arranged on the coverplate. A tile aligning and securing station where the tiles are aligned relative to each other and the coverplate by the tile aligner and where the tiles are at least partially bonded to the coverplate. A tile assembly bonding material dispensing station where a bonding material is applied to a surface of the tiles opposite the side that the coverplate is bonded to. A backplate placement station where a backplate is arranged on the tiles. A backplate aligning and securing station where the backplate is aligned with the tiles and the coverplate and at least partially secured to the tiles A full bonding station where the tiles are fully bonded to the coverplate and the backplate.

A signal to be scaled is supplied to three parallel amplifiers with gains of 0.1, 1, and 10, which each amplify the input simultaneously. The amplifiers are designed so that their output is limited to 1 volt regardless of the level of voltage at their input. This allows the lower magnitude portions of the signals to be amplified without amplifying the higher magnitude signals. The output of the amplifiers are summed together to provide the scaled signal.

Pseudo logarithmic analog step adder

Capacitance is measured using a system including a high voltage ramp monitor. A signal net is connected to ground by probes while a constant charging current is applied to the internal planes. A pure capacitive net will have a linear voltage rise proportional to capacitance, therefore its capacitance can be represented by ramp time. Leakage shorts will be detected by residual charge current measurements. The stimulus voltage is maintained for a fixed time after ramping to provide net to internal plane stress testing. Measured net capacitance is compared to nominal net capacitance for short/open detection.

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Newark Valley, NY, United States of America

Edward J Tasillo