Racal Data Communications Inc.

Edward J Sackman, Iii

Donald Lee Wray

Raul F Fernandez

David B Fallin

Juan E Farias

Craig A Lee

Dale R Jenkins

George A Clarke

Jon S Miller

Leroy D Young

A soft start circuit for hot installation of modules into an active bus. A very low R.sub.ds MOSFET provides bias through its drain to source path from a bus supply. This path is activated by a gate bias network which charges a capacitor from a supply located on the bus. Further control of the module supply is obtained by circuitry which permits addressing of the module to turn it off or on, temperature sensing to provide thermal protection and current sensing to provide short circuit protection.

Soft start circuit

A method and apparatus for providing communication among N modules connected to a common communication bus uses a bus structure with a reserve line for signaling the occurrence of a reservation time slot during which time each of the N modules which have information to transmit may reserve a time for transmission over the bus. A plurality of at least N data lines are used for transmission of data words over the bus. Each of the N modules are also assigned use of one of the plurality of data lines for signaling during the reservation time slot that the module has information to transmit over the bus. The reserve line is also used for signaling, that a word of data being transmitted over the plurality of data lines is a last word in a current transmission to be transmitted by the module currently transmitting.

High speed module interconnection bus

Disclosed is an arrangement having a main card cage, a plurality of remote card cages, and a data transport system for transmitting synchronous information, the data transport system having at least one bust electrically coupling the card cages to define a plurality of data lines between the main card cage and each of the remote card cages, a master clock generator at the main card cage for generating a single master clock, and a clock resynchronizer at the main card cage for resynchronizing with the master clock data messages received from the remote card cages which have the same frequency, but are shifted in phase from the master clock.

Clock resynchronization mechanism

An apparatus for controlling access to a time division multiplexed (TDM) bus includes a frame address register having a plurality of storage registers for storing a plurality of frame addresses designated for use in communicating over said TDM bus. A frame address latch stores a current frame address. A frame comparator, coupled to the frame address register and the frame address latch, compares the designated frame addresses with the current frame address and produces a first signal indicative of the storage register containing a frame address matching the current frame address. A time slot register has a plurality of storage registers for storing a time slot number designated for use in communicating over said TDM bus. A time slot generator generates a current time slot number. A time slot comparator, coupled to the time slot register and the time slot generator compares the designated time slot number with the current time slot number and produces a second signal indicative of the storage register containing a slot number matching the current time slot number. A token generator, coupled to the frame comparator and the time slot comparator receives the first and second signals and generates a token work unique to the first and second signals. A data transfer circuit transfers a data word to or from the TDM bus responsive to the token word.

Growing community of inventors

Sunrise, FL, United States of America

Edward J Sackman, Iii