Data General Corporation

Edward J Rasala

Michael L Ziegler

James Marriot Guyer

Michael B Druke

Kenneth D Holberger

Charles J Holland

Charles J Young

Richard W Coyle

Steven Wallach

Carl J Alsing

Thomas West

A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.

Data processing system

A digital data multiplier, particularly useful in floating point processing systems, wherein a first digital word representing a first value is multiplied by successive groups of bits of a second digital word representing a second value to form successive partial products which are combined to form successive partial sums, the final sum of all such combined partial sums producing a digital word representing the final product of the first and second values.

Floating point data processing system

Growing community of inventors

Westboro, MA, United States of America

Edward J Rasala