Unisys Corporation

Edward J Pullin

Gary C Wu

Philip A Murphy

Wayne A Genetti

Gunnar K Gunnarsson

Robert H Tickner

Chandra S Pawar

Steven A Thompson

Joseph C Duggan

Steven H Leibowitz

Michael J Hazzard

A microprocessor architecture that includes an arithmetic logic unit (ALU), a bit processing unit (BPU), a register file and an instruction register is disclosed. The BPU performs complex logical operations in a single clock cycle. The ALU continues to perform the slow arithmetic operations (e.g., multiply, divide). The BPU has two special purpose registers, a zero flag and a match flag, which are used for program execution control. The BPU performs bit manipulations on data stored in and received from the register file and/or individual fields in the instruction currently being executed by the BPU.

Bit processing unit for performing complex logical operations within a

A computer system performs memory to memory transfer, task scheduling and I/O request handling via a group of dedicated processors (e.g. a memory interface unit, an I/O unit, a data transfer unit, and a task control unit). The memory interface unit facilitates data interaction between the memory and the remainder of the system. The I/O unit is coupled to the memory interface unit and performs high level I/O job functions including I/O job scheduling, I/O job path selection, gathering of job statistics and device management. The data transfer unit is coupled to the memory interface unit and moves data between memory locations. The task control unit, coupled to the memory interface unit, allocates and deallocates events, maintains the status of tasks running on the system and schedules the execution of tasks. A hierarchical error reporting scheme is used by all of the processors.

Dedicated processor for task I/O and memory management

An apparatus for preventing bus contention among a plurality of data sources is described which creates signals to be used to disable two of three data sources which share a common bus immediately prior to a bus access cycle. The circuit employs a negative edge triggered flip-flop. This flip-flop generates disable signals which are shifted in phase by 90.degree. with respect to the bus access clock signal. These signals are active one-quarter of a clock cycle before a new bus cycle begins. The early disable serves to clear the bus for access by substantially eliminating the possibility that a slowly responding disabled data source is still active while a quickly responding enabled data source has just become active. The early disabling of the data signals does not result in loss of data. When all data sources on the bus are turned off, a high signal simply goes higher and a low signal rises slowly. The third data source and the disable circuitry for the other two sources are fabricated on the same integrated circuit to compensate for variations in speed from one circuit to the next.

Apparatus and method for preventing bus contention among a plurality of

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Norwood, PA, United States of America

Edward J Pullin