Newport Fab, LLC

Trieye Ltd.

Newport Fab, LLC Dba Jazz Semiconductor

Tower Semiconductor Ltd.

Edward J Preisler

Paul D Hurwitz

David J Howard

Marco Racanelli

Zhirong Tang

Kurt A Moen

Todd Thibeault

Difeng Zhu

Oleg Martynov

George Talor

Mantavya Sinha

Hadi Jebory

Gerson R Ortuno

Farnood Rezaie

Santosh Sharma

Samir Chaudhry

Uriel Levy

Omer Kapach

Avraham Bakal

Assaf Lahav

Jie Zheng

William Krieger

Yasir Qamar

A method of forming a semiconductor structure having a first substrate capable of electrically and mechanically connecting to a second substrate includes providing a first substrate without a solder bump. A solder bump receiving metal is formed over a top interconnect metal of the first substrate. The solder bump receiving metal may include platinum, a platinum alloy, nickel, or a nickel alloy. A passivation layer is formed, wherein the passivation layer is not situated under any portion of the solder bump receiving metal. A window is formed exposing a portion of the solder bump receiving metal. The method may further include providing a second substrate with a second substrate solder bump. The second substrate solder bump may be mechanically and electrically connecting to the exposed portion of the solder bump receiving metal of the first substrate.

Efficient integration of a first substrate without solder bumps with a second substrate having solder bumps

A stress-reduced silicon photonics semiconductor wafer includes a silicon nitride layer on a backside of the wafer. At least one silicon nitride stress-reduction configuration is on a topside of the wafer. At least one silicon nitride photonics device is also on the topside of the wafer. A silicon photonics device can be situated in the wafer.

Stress-reduced silicon photonics semiconductor wafer

A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.

Method for forming a semiconductor structure having a porous semiconductor layer in RF devices

A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Method of manufacturing bipolar complementary-metal-oxide-semiconductor (BiCMOS) devices using nickel silicide

A method of integrating an optoelectronic device comprising a Pockels material, such as lithium niobate (LiNbO3), includes forming an optoelectronic device layer over a semiconductor layer. The optoelectronic device layer includes a patterned optoelectronic device segment in an interlayer dielectric. A window is etched in the interlayer dielectric using the patterned optoelectronic device segment as a sacrificial etch stop. The patterned optoelectronic device segment is removed in the window. The optoelectronic device comprising the Pockels material is formed in place of the removed patterned optoelectronic device segment. The optoelectronic device comprising the Pockels material may be formed from an optoelectronic chiplet.

Integration of optoelectronic devices comprising lithium niobate or other Pockels materials

Method of manufacturing nickel silicide in bipolar complementary-metal-oxide-semiconductor (BiCMOS)

A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. Precursor stacks having at least one precursor metal are situated over at least one portion of the patterned group III-V device. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over each precursor stack. A filler metal is situated in each contact hole and over each precursor stack. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate. Additional contact holes in the blanket dielectric layer can be situated over the group IV devices and filled with the filler metals.

Group III-V device on group IV substrate using contacts with precursor stacks

A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over the patterned group III-V device. A liner stack having at least one metal liner is situated in each contact hole. Filler metals are situated over each liner stack and fill the contact holes. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate.

Method for manufacturing a semiconductor structure having group III-V device on group IV substrate and contacts with liner stacks

A semiconductor structure includes a group IV substrate including group IV dies separated by a scribe line. A group IIIV-chiplet is situated over the group IV substrate at least partially over the scribe line. A group III-V process control monitoring device in the group III-V chiplet is situated over the scribe line. Functional group III-V optoelectronic devices can be situated over the group IV dies.

Structure and method for process control monitoring for group III-V devices integrated with group IV substrate

A germanium-on-silicon photodetector is fabricated by forming a thin silicon oxide layer on a silicon layer, and then forming a silicon nitride layer on the silicon oxide layer. A nitride dry etch process is used to etch an opening through the silicon nitride layer (through a photoresist mask). The nitride dry etch is stopped on the thin silicon oxide layer, preventing damage to the underlying silicon layer. A wet etch is then performed through the opening in the silicon nitride layer to remove the exposed silicon oxide layer. The wet etch exposes (and cleans) a portion of the underlying silicon layer. High-quality germanium is epitaxially grown over the exposed portion of the silicon layer, thereby providing a germanium structure that forms the intrinsic region of a PIN photodiode.

Silicon nitride hard mask for epitaxial germanium on silicon

Semiconductor structure having group III-V device on group IV substrate and contacts with precursor stacks

Semiconductor structure having group III-V device on group IV substrate and contacts with liner stacks

A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. A blanket dielectric layer is situated over the patterned group III-V device. A contact metal is situated within the blanket dielectric layer and an interconnect metal is situated over the blanket dielectric layer. The blanket dielectric layer can be substantially planar. The contact metal and the interconnect metal can be electrically connected to the patterned group III-V device. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate.

Semiconductor structure having group III-V device on group IV substrate

A semiconductor structure includes a group III-V chiplet over a group IV substrate. A group IV optoelectronic device is situated in the group IV substrate. A patterned group III-V optoelectronic device is situated in the group III-V chiplet. A heating element is near the group IV optoelectronic device, or alternatively, near the patterned group III-V optoelectronic device. A dielectric layer is over the patterned group III-V optoelectronic device. A venting hole is in the dielectric layer in proximity of the heating element. A cavity is in the group IV substrate in proximity to the heating element.

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San Clemente, CA, United States of America

Edward J Preisler